From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2153) id DEFFC38618D7; Mon, 13 Jun 2022 08:54:34 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org DEFFC38618D7 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Jakub Jelinek To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-1061] i386: Fix up *3_doubleword_mask [PR105911] X-Act-Checkin: gcc X-Git-Author: Jakub Jelinek X-Git-Refname: refs/heads/master X-Git-Oldrev: 033e5ee3c4a2c841ff24e3bf3fc5324ea9cc373c X-Git-Newrev: 13ea4a6e830da1f245136601e636dec62e74d1a7 Message-Id: <20220613085434.DEFFC38618D7@sourceware.org> Date: Mon, 13 Jun 2022 08:54:34 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 13 Jun 2022 08:54:35 -0000 https://gcc.gnu.org/g:13ea4a6e830da1f245136601e636dec62e74d1a7 commit r13-1061-g13ea4a6e830da1f245136601e636dec62e74d1a7 Author: Jakub Jelinek Date: Mon Jun 13 10:53:33 2022 +0200 i386: Fix up *3_doubleword_mask [PR105911] Another regression caused by my recent patch. This time because define_insn_and_split only requires that the constant mask is const_int_operand. When it was only SImode, that wasn't a problem, HImode neither, but for DImode if we need to and the shift count we might run into a problem that it isn't a representable signed 32-bit immediate. But, we don't really care about the upper bits of the mask, so we can just mask the CONST_INT with the mode mask. 2022-06-13 Jakub Jelinek PR target/105911 * config/i386/i386.md (*ashl3_doubleword_mask, *3_doubleword_mask): Use operands[3] masked with ( * BITS_PER_UNIT) - 1 as AND operand instead of operands[3] unmodified. * gcc.dg/pr105911.c: New test. Diff: --- gcc/config/i386/i386.md | 6 ++++-- gcc/testsuite/gcc.dg/pr105911.c | 16 ++++++++++++++++ 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 5b538413942..3093cb513b9 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -11937,7 +11937,8 @@ rtx xops[3]; xops[0] = gen_reg_rtx (GET_MODE (operands[2])); xops[1] = operands[2]; - xops[2] = operands[3]; + xops[2] = GEN_INT (INTVAL (operands[3]) + & (( * BITS_PER_UNIT) - 1)); ix86_expand_binary_operator (AND, GET_MODE (operands[2]), xops); operands[2] = xops[0]; } @@ -12905,7 +12906,8 @@ rtx xops[3]; xops[0] = gen_reg_rtx (GET_MODE (operands[2])); xops[1] = operands[2]; - xops[2] = operands[3]; + xops[2] = GEN_INT (INTVAL (operands[3]) + & (( * BITS_PER_UNIT) - 1)); ix86_expand_binary_operator (AND, GET_MODE (operands[2]), xops); operands[2] = xops[0]; } diff --git a/gcc/testsuite/gcc.dg/pr105911.c b/gcc/testsuite/gcc.dg/pr105911.c new file mode 100644 index 00000000000..55df3f15aff --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr105911.c @@ -0,0 +1,16 @@ +/* PR target/105911 */ +/* { dg-do compile { target int128 } } */ +/* { dg-options "-O2" } */ + +__int128 v, x; +unsigned __int128 w; + +void bar (__int128, __int128); + +void +foo (void) +{ + bar (v /= v, v >> (v &= 0x100000001)); + bar (w /= w, w >> (w &= 0x300000003)); + bar (x /= x, x << (x &= 0x700000007)); +}