From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1923) id D4FB0386DC7C; Tue, 14 Jun 2022 11:38:22 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D4FB0386DC7C MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Philipp Tomsich To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-1088] RISC-V: Split slli+sh[123]add.uw opportunities to avoid zext.w X-Act-Checkin: gcc X-Git-Author: Philipp Tomsich X-Git-Refname: refs/heads/master X-Git-Oldrev: 4bf0dcb0492c40be7e0603b13a8b5949609388dd X-Git-Newrev: 0247ad3e0f4a574273b42344fbaa9346599948f9 Message-Id: <20220614113822.D4FB0386DC7C@sourceware.org> Date: Tue, 14 Jun 2022 11:38:22 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 14 Jun 2022 11:38:22 -0000 https://gcc.gnu.org/g:0247ad3e0f4a574273b42344fbaa9346599948f9 commit r13-1088-g0247ad3e0f4a574273b42344fbaa9346599948f9 Author: Philipp Tomsich Date: Wed May 11 12:12:57 2022 +0200 RISC-V: Split slli+sh[123]add.uw opportunities to avoid zext.w When encountering a prescaled (biased) value as a candidate for sh[123]add.uw, the combine pass will present this as shifted by the aggregate amount (prescale + shift-amount) with an appropriately adjusted mask constant that has fewer than 32 bits set. E.g., here's the failing expression seen in combine for a prescale of 1 and a shift of 2 (note how 0x3fffffff8 >> 3 is 0x7fffffff). Trying 7, 8 -> 10: 7: r78:SI=r81:DI#0<<0x1 REG_DEAD r81:DI 8: r79:DI=zero_extend(r78:SI) REG_DEAD r78:SI 10: r80:DI=r79:DI<<0x2+r82:DI REG_DEAD r79:DI REG_DEAD r82:DI Failed to match this instruction: (set (reg:DI 80 [ cD.1491 ]) (plus:DI (and:DI (ashift:DI (reg:DI 81) (const_int 3 [0x3])) (const_int 17179869176 [0x3fffffff8])) (reg:DI 82))) To address this, we introduce a splitter handling these cases. Signed-off-by: Philipp Tomsich Co-developed-by: Manolis Tsamis gcc/ChangeLog: * config/riscv/bitmanip.md: Add split to handle opportunities for slli + sh[123]add.uw gcc/testsuite/ChangeLog: * gcc.target/riscv/zba-shadd.c: New test. Diff: --- gcc/config/riscv/bitmanip.md | 44 ++++++++++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/zba-shadd.c | 13 +++++++++ 2 files changed, 57 insertions(+) diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index 0ab9ffe3c0b..6c1ccc6f8c5 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -79,6 +79,50 @@ [(set_attr "type" "bitmanip") (set_attr "mode" "DI")]) +;; During combine, we may encounter an attempt to combine +;; slli rtmp, rs, #imm +;; zext.w rtmp, rtmp +;; sh[123]add rd, rtmp, rs2 +;; which will lead to the immediate not satisfying the above constraints. +;; By splitting the compound expression, we can simplify to a slli and a +;; sh[123]add.uw. +(define_split + [(set (match_operand:DI 0 "register_operand") + (plus:DI (and:DI (ashift:DI (match_operand:DI 1 "register_operand") + (match_operand:QI 2 "immediate_operand")) + (match_operand:DI 3 "consecutive_bits_operand")) + (match_operand:DI 4 "register_operand"))) + (clobber (match_operand:DI 5 "register_operand"))] + "TARGET_64BIT && TARGET_ZBA" + [(set (match_dup 5) (ashift:DI (match_dup 1) (match_dup 6))) + (set (match_dup 0) (plus:DI (and:DI (ashift:DI (match_dup 5) + (match_dup 7)) + (match_dup 8)) + (match_dup 4)))] +{ + unsigned HOST_WIDE_INT mask = UINTVAL (operands[3]); + /* scale: shift within the sh[123]add.uw */ + int scale = 32 - clz_hwi (mask); + /* bias: pre-scale amount (i.e. the prior shift amount) */ + int bias = ctz_hwi (mask) - scale; + + /* If the bias + scale don't add up to operand[2], reject. */ + if ((scale + bias) != UINTVAL (operands[2])) + FAIL; + + /* If the shift-amount is out-of-range for sh[123]add.uw, reject. */ + if ((scale < 1) || (scale > 3)) + FAIL; + + /* If there's no bias, the '*shNadduw' pattern should have matched. */ + if (bias == 0) + FAIL; + + operands[6] = GEN_INT (bias); + operands[7] = GEN_INT (scale); + operands[8] = GEN_INT (0xffffffffULL << scale); +}) + (define_insn "*add.uw" [(set (match_operand:DI 0 "register_operand" "=r") (plus:DI (zero_extend:DI diff --git a/gcc/testsuite/gcc.target/riscv/zba-shadd.c b/gcc/testsuite/gcc.target/riscv/zba-shadd.c new file mode 100644 index 00000000000..33da2530f3f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zba-shadd.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64gc_zba -mabi=lp64" } */ + +unsigned long foo(unsigned int a, unsigned long b) +{ + a = a << 1; + unsigned long c = (unsigned long) a; + unsigned long d = b + (c<<2); + return d; +} + +/* { dg-final { scan-assembler "sh2add.uw" } } */ +/* { dg-final { scan-assembler-not "zext" } } */ \ No newline at end of file