From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1880) id D57AB385627D; Wed, 15 Jun 2022 23:59:36 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D57AB385627D MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Max Filippov To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-1123] xtensa: Eliminate unwanted reg-reg moves during DFmode input reloads X-Act-Checkin: gcc X-Git-Author: Takayuki 'January June' Suwa X-Git-Refname: refs/heads/master X-Git-Oldrev: c95e307e3a978166cd5d6817ec9d8293825ff3fb X-Git-Newrev: cfad4856fa46abc878934a9433d0bfc2482ccf00 Message-Id: <20220615235936.D57AB385627D@sourceware.org> Date: Wed, 15 Jun 2022 23:59:36 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 15 Jun 2022 23:59:36 -0000 https://gcc.gnu.org/g:cfad4856fa46abc878934a9433d0bfc2482ccf00 commit r13-1123-gcfad4856fa46abc878934a9433d0bfc2482ccf00 Author: Takayuki 'January June' Suwa Date: Tue Jun 14 12:39:49 2022 +0900 xtensa: Eliminate unwanted reg-reg moves during DFmode input reloads When spilled DFmode registers are reloaded in, once loaded into a pair of SImode regs and then copied from that regs. Such unwanted reg-reg moves seems not to be eliminated at the "cprop_hardreg" stage, despite no problem in output reloads. Luckily it is easy to resolve such inefficiencies, with the use of peephole2 pattern. gcc/ChangeLog: * config/xtensa/predicates.md (reload_operand): New predicate. * config/xtensa/xtensa.md: New peephole2 pattern. Diff: --- gcc/config/xtensa/predicates.md | 13 +++++++++++++ gcc/config/xtensa/xtensa.md | 31 +++++++++++++++++++++++++++++++ 2 files changed, 44 insertions(+) diff --git a/gcc/config/xtensa/predicates.md b/gcc/config/xtensa/predicates.md index d63a6cf034c..edd13ae41b9 100644 --- a/gcc/config/xtensa/predicates.md +++ b/gcc/config/xtensa/predicates.md @@ -165,6 +165,19 @@ (and (match_code "const_int") (match_test "xtensa_mem_offset (INTVAL (op), SFmode)"))) +(define_predicate "reload_operand" + (match_code "mem") +{ + const_rtx addr = XEXP (op, 0); + if (REG_P (addr)) + return REGNO (addr) == A1_REG; + if (GET_CODE (addr) == PLUS) + return REG_P (XEXP (addr, 0)) + && REGNO (XEXP (addr, 0)) == A1_REG + && CONST_INT_P (XEXP (addr, 1)); + return false; +}) + (define_predicate "branch_operator" (match_code "eq,ne,lt,ge")) diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md index fa2a4a05a25..8ed0ff53a70 100644 --- a/gcc/config/xtensa/xtensa.md +++ b/gcc/config/xtensa/xtensa.md @@ -2749,3 +2749,34 @@ (if_then_else (match_test "TARGET_DENSITY") (const_int 5) (const_int 6)))]) + +(define_peephole2 + [(set (match_operand:SI 0 "register_operand") + (match_operand:SI 6 "reload_operand")) + (set (match_operand:SI 1 "register_operand") + (match_operand:SI 7 "reload_operand")) + (set (match_operand:SF 2 "register_operand") + (match_operand:SF 4 "register_operand")) + (set (match_operand:SF 3 "register_operand") + (match_operand:SF 5 "register_operand"))] + "REGNO (operands[0]) == REGNO (operands[4]) + && REGNO (operands[1]) == REGNO (operands[5]) + && peep2_reg_dead_p (4, operands[0]) + && peep2_reg_dead_p (4, operands[1])" + [(set (match_dup 2) + (match_dup 6)) + (set (match_dup 3) + (match_dup 7))] +{ + uint32_t check = 0; + int i; + for (i = 0; i <= 3; ++i) + { + uint32_t mask = (uint32_t)1 << REGNO (operands[i]); + if (check & mask) + FAIL; + check |= mask; + } + operands[6] = gen_rtx_MEM (SFmode, XEXP (operands[6], 0)); + operands[7] = gen_rtx_MEM (SFmode, XEXP (operands[7], 0)); +})