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* [gcc(refs/vendors/ARM/heads/morello)] morello: add Morello ACLE builtins
@ 2022-06-16 10:07 Przemyslaw Wirkus
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From: Przemyslaw Wirkus @ 2022-06-16 10:07 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:f943dc5219f965d5263c920ddc3d51b5feaa5116
commit f943dc5219f965d5263c920ddc3d51b5feaa5116
Author: Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
Date: Thu Jun 16 10:54:28 2022 +0100
morello: add Morello ACLE builtins
This patch is adding set of Morello ACLE builtins, see [0]:
__builtin_morello_chkssu builtin.
__builtin_morello_cvtz builtin.
__builtin_morello_subset_test_unseal_or_null
Also new pattern `cmovcadi_insn` is added to support CSEL for Morello
ISA.
[0] https://github.com/ARM-software/acle/blob/main/morello/morello.md#builtin-functions
gcc/ChangeLog:
* config/aarch64/aarch64-builtins.c (enum aarch64_builtins): New builtin
enums.
(aarch64_init_morello_builtins): New
(aarch64_expand_morello_builtin): New builtin expands.
(aarch64_general_expand_builtin): Handle new builtins.
* config/aarch64/aarch64-morello.md: New patterns.
* config/aarch64/aarch64.md: New unspecs defined
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/morello/builtin_morello_chkssu.c: New test.
* gcc.target/aarch64/morello/builtin_morello_cvtz.c: New test.
* gcc.target/aarch64/morello/builtin_morello_subset_test_unseal_or_null.c: New
test.
Diff:
---
gcc/config/aarch64/aarch64-builtins.c | 49 +++++++++++++++++++
gcc/config/aarch64/aarch64-morello.md | 56 ++++++++++++++++++++++
gcc/config/aarch64/aarch64.md | 3 ++
.../aarch64/morello/builtin_morello_chkssu.c | 9 ++++
.../aarch64/morello/builtin_morello_cvtz.c | 12 +++++
.../builtin_morello_subset_test_unseal_or_null.c | 10 ++++
6 files changed, 139 insertions(+)
diff --git a/gcc/config/aarch64/aarch64-builtins.c b/gcc/config/aarch64/aarch64-builtins.c
index 49f308ac507..31a9167111c 100644
--- a/gcc/config/aarch64/aarch64-builtins.c
+++ b/gcc/config/aarch64/aarch64-builtins.c
@@ -499,12 +499,15 @@ enum aarch64_builtins
AARCH64_MORELLO_BUILTIN_PC_GET,
AARCH64_MORELLO_BUILTIN_PERMS_AND,
AARCH64_MORELLO_BUILTIN_PERMS_GET,
+ AARCH64_MORELLO_BUILTIN_PTR_TO_CAP_OFFSET,
AARCH64_MORELLO_BUILTIN_REPR_ALIGNMENT_MASK,
AARCH64_MORELLO_BUILTIN_ROUND_REPR_LEN,
AARCH64_MORELLO_BUILTIN_SEAL,
AARCH64_MORELLO_BUILTIN_SEAL_ENTRY,
AARCH64_MORELLO_BUILTIN_SEALED_GET,
+ AARCH64_MORELLO_BUILTIN_SUBSET_CHECK,
AARCH64_MORELLO_BUILTIN_SUBSET_TEST,
+ AARCH64_MORELLO_BUILTIN_SUBSET_TEST_UNSEAL_OR_NULL,
AARCH64_MORELLO_BUILTIN_TAG_CLEAR,
AARCH64_MORELLO_BUILTIN_TAG_GET,
AARCH64_MORELLO_BUILTIN_TYPE_GET,
@@ -1585,6 +1588,18 @@ aarch64_init_morello_builtins (void)
AARCH64_MORELLO_BUILTIN_UNSEAL,
build_function_type_list (cap_type_node, cap_type_node,
cap_type_node, NULL_TREE)},
+ {"__builtin_morello_chkssu",
+ AARCH64_MORELLO_BUILTIN_SUBSET_CHECK,
+ build_function_type_list (cap_type_node, const_cap_type_node,
+ const_cap_type_node, NULL_TREE)},
+ {"__builtin_morello_cvtz",
+ AARCH64_MORELLO_BUILTIN_PTR_TO_CAP_OFFSET,
+ build_function_type_list (cap_type_node, const_cap_type_node,
+ size_type_node, NULL_TREE)},
+ {"__builtin_morello_subset_test_unseal_or_null",
+ AARCH64_MORELLO_BUILTIN_SUBSET_TEST_UNSEAL_OR_NULL,
+ build_function_type_list (cap_type_node, const_cap_type_node,
+ const_cap_type_node, NULL_TREE)},
};
for (size_t i = 0; i < ARRAY_SIZE (data); ++i)
@@ -2430,6 +2445,16 @@ aarch64_expand_morello_builtin (tree exp, rtx target, int fcode)
expand_insn (CODE_FOR_aarch64_cap_pc_get, 1, ops);
return ops[0].value;
}
+ case AARCH64_MORELLO_BUILTIN_PTR_TO_CAP_OFFSET:
+ {
+ rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
+ rtx op1 = expand_normal (CALL_EXPR_ARG (exp, 1));
+ create_output_operand (&ops[0], target, CADImode);
+ create_input_operand (&ops[1], op0, CADImode);
+ create_input_operand (&ops[2], op1, DImode);
+ expand_insn (CODE_FOR_aarch64_ptr_to_cap_offset_cadi, 3, ops);
+ return ops[0].value;
+ }
case AARCH64_MORELLO_BUILTIN_REPR_ALIGNMENT_MASK:
{
rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
@@ -2472,6 +2497,16 @@ aarch64_expand_morello_builtin (tree exp, rtx target, int fcode)
expand_insn (CODE_FOR_aarch64_cap_sealed_get, 2, ops);
return ops[0].value;
}
+ case AARCH64_MORELLO_BUILTIN_SUBSET_CHECK:
+ {
+ rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
+ rtx op1 = expand_normal (CALL_EXPR_ARG (exp, 1));
+ create_output_operand (&ops[0], target, CADImode);
+ create_input_operand (&ops[1], op0, CADImode);
+ create_input_operand (&ops[2], op1, CADImode);
+ expand_insn (CODE_FOR_aarch64_cap_subset_check_cadi, 3, ops);
+ return ops[0].value;
+ }
case AARCH64_MORELLO_BUILTIN_SUBSET_TEST:
{
rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
@@ -2482,6 +2517,17 @@ aarch64_expand_morello_builtin (tree exp, rtx target, int fcode)
expand_insn (CODE_FOR_aarch64_cap_subset_test, 3, ops);
return ops[0].value;
}
+ case AARCH64_MORELLO_BUILTIN_SUBSET_TEST_UNSEAL_OR_NULL:
+ {
+ rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
+ rtx op1 = expand_normal (CALL_EXPR_ARG (exp, 1));
+ create_output_operand (&ops[0], target, CADImode);
+ create_input_operand (&ops[1], op0, CADImode);
+ create_input_operand (&ops[2], op1, CADImode);
+ expand_insn (CODE_FOR_aarch64_cap_subset_test_unseal_or_null_cadi,
+ 3, ops);
+ return ops[0].value;
+ }
case AARCH64_MORELLO_BUILTIN_TAG_CLEAR:
{
rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
@@ -2650,12 +2696,15 @@ aarch64_general_expand_builtin (unsigned int fcode, tree exp, rtx target,
case AARCH64_MORELLO_BUILTIN_PC_GET:
case AARCH64_MORELLO_BUILTIN_PERMS_AND:
case AARCH64_MORELLO_BUILTIN_PERMS_GET:
+ case AARCH64_MORELLO_BUILTIN_PTR_TO_CAP_OFFSET:
case AARCH64_MORELLO_BUILTIN_REPR_ALIGNMENT_MASK:
case AARCH64_MORELLO_BUILTIN_ROUND_REPR_LEN:
case AARCH64_MORELLO_BUILTIN_SEAL:
case AARCH64_MORELLO_BUILTIN_SEALED_GET:
case AARCH64_MORELLO_BUILTIN_SEAL_ENTRY:
+ case AARCH64_MORELLO_BUILTIN_SUBSET_CHECK:
case AARCH64_MORELLO_BUILTIN_SUBSET_TEST:
+ case AARCH64_MORELLO_BUILTIN_SUBSET_TEST_UNSEAL_OR_NULL:
case AARCH64_MORELLO_BUILTIN_TAG_CLEAR:
case AARCH64_MORELLO_BUILTIN_TAG_GET:
case AARCH64_MORELLO_BUILTIN_TYPE_GET:
diff --git a/gcc/config/aarch64/aarch64-morello.md b/gcc/config/aarch64/aarch64-morello.md
index a21005ee25a..a27234b220d 100644
--- a/gcc/config/aarch64/aarch64-morello.md
+++ b/gcc/config/aarch64/aarch64-morello.md
@@ -492,3 +492,59 @@
"TARGET_MORELLO"
"cfhi\\t%0, %1"
)
+
+(define_insn "aarch64_cap_subset_check_cadi"
+ [(set (reg:CC_N CC_REGNUM)
+ (unspec:CC_N [(match_operand:CADI 1 "register_operand" "rk")
+ (match_operand:CADI 2 "register_operand" "rk")]
+ UNSPEC_CHERI_SUBSET_CHECK_INNER))
+ (set (match_operand:CADI 0 "register_operand" "=r")
+ (unspec:CADI [(match_dup 1)
+ (match_dup 2)]
+ UNSPEC_CHERI_SUBSET_CHECK))]
+ "TARGET_MORELLO"
+ "chkssu\\t%0, %1, %2"
+)
+
+(define_insn "aarch64_ptr_to_cap_offset_cadi"
+ [(set (match_operand:CADI 0 "register_operand" "=r")
+ (unspec:CADI [(match_operand:CADI 1 "register_operand" "rk")
+ (match_operand:DI 2 "register_operand" "r")]
+ UNSPEC_CHERI_PTR_TO_CAP_OFFSET))
+ ]
+ "TARGET_MORELLO"
+ "cvtz\\t%0, %1, %2"
+)
+
+(define_insn "cmovcadi_insn"
+ [(set (match_operand:CADI 0 "register_operand" "=r,r,r")
+ (if_then_else:CADI
+ (match_operator 1 "aarch64_comparison_operator"
+ [(match_operand 2 "cc_register" "") (const_int 0)])
+ (match_operand:CADI 3 "aarch64_reg_or_zero" "r,r,Z")
+ (match_operand:CADI 4 "aarch64_reg_or_zero" "r,Z,r")))]
+ "TARGET_MORELLO"
+ "@
+ csel\\t%0, %3, %4, %m1
+ csel\\t%0, %3, czr, %m1
+ csel\\t%0, %4, czr, %m1"
+ [(set_attr "type" "csel, csel, csel")]
+)
+
+(define_expand "aarch64_cap_subset_test_unseal_or_null_cadi"
+ [(match_operand:CADI 0 "register_operand")
+ (match_operand:CADI 1 "register_operand")
+ (match_operand:CADI 2 "register_operand")]
+ "TARGET_MORELLO"
+ {
+ rtx chkssu = gen_aarch64_cap_subset_check_cadi (operands[0], operands[1],
+ operands[2]);
+ emit_insn (chkssu);
+ rtx cc = gen_rtx_REG (CCmode, CC_REGNUM);
+ rtx cmp_res = gen_reg_rtx (SImode);
+ rtx compare_neg = gen_rtx_LT (GET_MODE(cmp_res), cmp_res, const0_rtx);
+ emit_insn (gen_cmovcadi_insn (operands[0], compare_neg, cc, operands[0],
+ const0_rtx));
+ DONE;
+ }
+)
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 06f596bc3e7..3395a634edb 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -156,11 +156,14 @@
UNSPEC_CHERI_OFFSET_INC
UNSPEC_CHERI_OFFSET_SET
UNSPEC_CHERI_PERMS_GET
+ UNSPEC_CHERI_PTR_TO_CAP_OFFSET
UNSPEC_CHERI_REPR_ALIGN_MASK
UNSPEC_CHERI_ROUND_REPR_LEN
UNSPEC_CHERI_SEAL
UNSPEC_CHERI_SEAL_ENTRY
UNSPEC_CHERI_SEALED_GET
+ UNSPEC_CHERI_SUBSET_CHECK
+ UNSPEC_CHERI_SUBSET_CHECK_INNER
UNSPEC_CHERI_SUBSET_TEST
UNSPEC_CHERI_TAG_CLEAR
UNSPEC_CHERI_TAG_GET
diff --git a/gcc/testsuite/gcc.target/aarch64/morello/builtin_morello_chkssu.c b/gcc/testsuite/gcc.target/aarch64/morello/builtin_morello_chkssu.c
new file mode 100644
index 00000000000..bc8133d7e7a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/morello/builtin_morello_chkssu.c
@@ -0,0 +1,9 @@
+/* { dg-do compile { target aarch64*-*-* } } */
+/* { dg-additional-options "-march=morello+c64 -mabi=purecap" } */
+
+void * __capability
+foo (void* __capability a, void* __capability b) {
+ return __builtin_morello_chkssu (a, b);
+}
+
+/* { dg-final { scan-assembler-times {chkssu\tc[0-9]+, c[0-9]+, c[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/morello/builtin_morello_cvtz.c b/gcc/testsuite/gcc.target/aarch64/morello/builtin_morello_cvtz.c
new file mode 100644
index 00000000000..47478cd23eb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/morello/builtin_morello_cvtz.c
@@ -0,0 +1,12 @@
+/* { dg-do compile { target aarch64*-*-* } } */
+/* { dg-additional-options "-march=morello+c64 -mabi=purecap" } */
+
+typedef unsigned long size_t;
+
+void* __capability
+bar (void* __capability a, size_t b) {
+ return __builtin_morello_cvtz (a, b);
+}
+
+/* { dg-final { scan-assembler-times {cvtz\tc[0-9]+, c[0-9]+, x[0-9]+} 1 } } */
+
diff --git a/gcc/testsuite/gcc.target/aarch64/morello/builtin_morello_subset_test_unseal_or_null.c b/gcc/testsuite/gcc.target/aarch64/morello/builtin_morello_subset_test_unseal_or_null.c
new file mode 100644
index 00000000000..b00f7717e9f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/morello/builtin_morello_subset_test_unseal_or_null.c
@@ -0,0 +1,10 @@
+/* { dg-do compile { target aarch64*-*-* } } */
+/* { dg-additional-options "-march=morello+c64 -mabi=purecap" } */
+
+void *__capability
+foo (const void *__capability a, const void *__capability b) {
+ return __builtin_morello_subset_test_unseal_or_null (a, b);
+}
+
+/* { dg-final { scan-assembler-times {chkssu\tc[0-9]+, c[0-9]+, c[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {csel\t} 1 } } */
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2022-06-16 10:07 [gcc(refs/vendors/ARM/heads/morello)] morello: add Morello ACLE builtins Przemyslaw Wirkus
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