From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1363) id 52BB83857B8B; Mon, 20 Jun 2022 20:53:53 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 52BB83857B8B MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset="utf-8" From: Uros Bizjak To: gcc-cvs@gcc.gnu.org Subject: [gcc r10-10861] alpha: Introduce target specific store_data_bypass_p function [PR105209] X-Act-Checkin: gcc X-Git-Author: Uros Bizjak X-Git-Refname: refs/heads/releases/gcc-10 X-Git-Oldrev: 570a6067ff6928fe76bb13cece38346d9a966a13 X-Git-Newrev: 94cf9bfb4d269fa5a4e3eeda45f4eafe392bfd58 Message-Id: <20220620205353.52BB83857B8B@sourceware.org> Date: Mon, 20 Jun 2022 20:53:53 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 20 Jun 2022 20:53:53 -0000 https://gcc.gnu.org/g:94cf9bfb4d269fa5a4e3eeda45f4eafe392bfd58 commit r10-10861-g94cf9bfb4d269fa5a4e3eeda45f4eafe392bfd58 Author: Uros Bizjak Date: Fri Jun 17 17:19:44 2022 +0200 alpha: Introduce target specific store_data_bypass_p function [PR105209] This patch introduces alpha-specific version of store_data_bypass_p that ignores TRAP_IF that would result in assertion failure (and internal compiler error) in the generic store_data_bypass_p function. While at it, also remove ev4_ist_c reservation, store_data_bypass_p can handle the patterns with multiple sets since some time ago. 2022-06-17 Uroš Bizjak gcc/ChangeLog: PR target/105209 * config/alpha/alpha-protos.h (alpha_store_data_bypass_p): New. * config/alpha/alpha.c (alpha_store_data_bypass_p): New function. (alpha_store_data_bypass_p_1): Ditto. * config/alpha/ev4.md: Use alpha_store_data_bypass_p instead of generic store_data_bypass_p. (ev4_ist_c): Remove insn reservation. gcc/testsuite/ChangeLog: PR target/105209 * gcc.target/alpha/pr105209.c: New test. (cherry picked from commit cc378e655740e93743e7f43e14faaff707aef6c1) Diff: --- gcc/config/alpha/alpha-protos.h | 2 + gcc/config/alpha/alpha.c | 69 +++++++++++++++++++++++++++++++ gcc/config/alpha/ev4.md | 15 ++----- gcc/testsuite/gcc.target/alpha/pr105209.c | 26 ++++++++++++ 4 files changed, 101 insertions(+), 11 deletions(-) diff --git a/gcc/config/alpha/alpha-protos.h b/gcc/config/alpha/alpha-protos.h index ba4cb3bf9cd..a3b437295cc 100644 --- a/gcc/config/alpha/alpha-protos.h +++ b/gcc/config/alpha/alpha-protos.h @@ -73,6 +73,8 @@ extern void alpha_end_function (FILE *, const char *, tree); extern bool alpha_find_lo_sum_using_gp (rtx); +extern int alpha_store_data_bypass_p (rtx_insn *, rtx_insn *); + #ifdef REAL_VALUE_TYPE extern int check_float_value (machine_mode, REAL_VALUE_TYPE *, int); #endif diff --git a/gcc/config/alpha/alpha.c b/gcc/config/alpha/alpha.c index 49b5a24d4b0..fb0738eb8b2 100644 --- a/gcc/config/alpha/alpha.c +++ b/gcc/config/alpha/alpha.c @@ -7564,6 +7564,75 @@ alpha_does_function_need_gp (void) return 0; } +/* Helper function for alpha_store_data_bypass_p, handle just a single SET + IN_SET. */ + +static bool +alpha_store_data_bypass_p_1 (rtx_insn *out_insn, rtx in_set) +{ + if (!MEM_P (SET_DEST (in_set))) + return false; + + rtx out_set = single_set (out_insn); + if (out_set) + return !reg_mentioned_p (SET_DEST (out_set), SET_DEST (in_set)); + + rtx out_pat = PATTERN (out_insn); + if (GET_CODE (out_pat) != PARALLEL) + return false; + + for (int i = 0; i < XVECLEN (out_pat, 0); i++) + { + rtx out_exp = XVECEXP (out_pat, 0, i); + + if (GET_CODE (out_exp) == CLOBBER || GET_CODE (out_exp) == USE + || GET_CODE (out_exp) == TRAP_IF) + continue; + + gcc_assert (GET_CODE (out_exp) == SET); + + if (reg_mentioned_p (SET_DEST (out_exp), SET_DEST (in_set))) + return false; + } + + return true; +} + +/* True if the dependency between OUT_INSN and IN_INSN is on the store + data not the address operand(s) of the store. IN_INSN and OUT_INSN + must be either a single_set or a PARALLEL with SETs inside. + + This alpha-specific version of store_data_bypass_p ignores TRAP_IF + that would result in assertion failure (and internal compiler error) + in the generic store_data_bypass_p function. */ + +int +alpha_store_data_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn) +{ + rtx in_set = single_set (in_insn); + if (in_set) + return alpha_store_data_bypass_p_1 (out_insn, in_set); + + rtx in_pat = PATTERN (in_insn); + if (GET_CODE (in_pat) != PARALLEL) + return false; + + for (int i = 0; i < XVECLEN (in_pat, 0); i++) + { + rtx in_exp = XVECEXP (in_pat, 0, i); + + if (GET_CODE (in_exp) == CLOBBER || GET_CODE (in_exp) == USE + || GET_CODE (in_exp) == TRAP_IF) + continue; + + gcc_assert (GET_CODE (in_exp) == SET); + + if (!alpha_store_data_bypass_p_1 (out_insn, in_exp)) + return false; + } + + return true; +} /* Helper function to set RTX_FRAME_RELATED_P on instructions, including sequences. */ diff --git a/gcc/config/alpha/ev4.md b/gcc/config/alpha/ev4.md index c6dfaa05406..ba5ce964937 100644 --- a/gcc/config/alpha/ev4.md +++ b/gcc/config/alpha/ev4.md @@ -44,14 +44,7 @@ ; Stores can issue before the data (but not address) is ready. (define_insn_reservation "ev4_ist" 1 (and (eq_attr "tune" "ev4") - (eq_attr "type" "ist")) - "ev4_ib1+ev4_abox") - -; ??? Separate from ev4_ist because store_data_bypass_p can't handle -; the patterns with multiple sets, like store-conditional. -(define_insn_reservation "ev4_ist_c" 1 - (and (eq_attr "tune" "ev4") - (eq_attr "type" "st_c")) + (eq_attr "type" "ist,st_c")) "ev4_ib1+ev4_abox") (define_insn_reservation "ev4_fst" 1 @@ -110,7 +103,7 @@ (define_bypass 0 "ev4_iaddlog,ev4_shiftcm,ev4_icmp" "ev4_ist" - "store_data_bypass_p") + "alpha_store_data_bypass_p") ; Multiplies use a non-pipelined imul unit. Also, "no [ebox] insn can ; be issued exactly three cycles before an integer multiply completes". @@ -121,7 +114,7 @@ (eq_attr "opsize" "si"))) "ev4_ib0+ev4_imul,ev4_imul*18,ev4_ebox") -(define_bypass 20 "ev4_imulsi" "ev4_ist" "store_data_bypass_p") +(define_bypass 20 "ev4_imulsi" "ev4_ist" "alpha_store_data_bypass_p") (define_insn_reservation "ev4_imuldi" 23 (and (eq_attr "tune" "ev4") @@ -129,7 +122,7 @@ (eq_attr "opsize" "!si"))) "ev4_ib0+ev4_imul,ev4_imul*20,ev4_ebox") -(define_bypass 22 "ev4_imuldi" "ev4_ist" "store_data_bypass_p") +(define_bypass 22 "ev4_imuldi" "ev4_ist" "alpha_store_data_bypass_p") ; Most FP insns have a 6 cycle latency, but with a 4 cycle bypass back in. (define_insn_reservation "ev4_fpop" 6 diff --git a/gcc/testsuite/gcc.target/alpha/pr105209.c b/gcc/testsuite/gcc.target/alpha/pr105209.c new file mode 100644 index 00000000000..b89be96dc1d --- /dev/null +++ b/gcc/testsuite/gcc.target/alpha/pr105209.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftrapv -mcpu=ev4" } */ + +typedef struct tnode_t { + struct tnode_t *tn_left, *tn_right; + int v_quad; +} tnode_t; + +int constant_addr(const tnode_t *, long *); +int constant_addr(const tnode_t *tn, long *offsp) +{ + long offs1 = 0, offs2 = 0; + + if (tn->v_quad > 0) { + offs1 = tn->v_quad; + return 0; + } else if (tn->v_quad > -1) { + offs2 = tn->tn_right->v_quad; + if (!constant_addr(tn->tn_left, &offs1)) + return 0; + } else { + return 0; + } + *offsp = offs1 + offs2; + return 1; +}