From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1251) id CA71F3851154; Sun, 3 Jul 2022 13:02:25 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org CA71F3851154 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Roger Sayle To: gcc-cvs@gcc.gnu.org Subject: [gcc r12-8542] PR target/106122: Don't update %esp via the stack with -Oz on x86. X-Act-Checkin: gcc X-Git-Author: Roger Sayle X-Git-Refname: refs/heads/releases/gcc-12 X-Git-Oldrev: a60152e87cc0900ed01854cdda8c2be6aab34af2 X-Git-Newrev: 55899e33de74082521708a58fdc79510e0c5efad Message-Id: <20220703130225.CA71F3851154@sourceware.org> Date: Sun, 3 Jul 2022 13:02:25 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 03 Jul 2022 13:02:25 -0000 https://gcc.gnu.org/g:55899e33de74082521708a58fdc79510e0c5efad commit r12-8542-g55899e33de74082521708a58fdc79510e0c5efad Author: Roger Sayle Date: Sun Jul 3 14:01:17 2022 +0100 PR target/106122: Don't update %esp via the stack with -Oz on x86. When optimizing for size with -Oz, setting a register can be minimized by pushing an immediate value to the stack and popping it to the destination. Alas the one general register that shouldn't be updated via the stack is the stack pointer itself, where "pop %esp" can't be represented in GCC's RTL ("use of a register mentioned in pre_inc, pre_dec, post_inc or post_dec is not permitted within the same instruction"). This patch fixes PR target/106122 by explicitly checking for SP_REG in the problematic peephole2. 2022-07-O3 Roger Sayle gcc/ChangeLog PR target/106122 * config/i386/i386.md (peephole2): Avoid generating pop %esp when optimizing for size. gcc/testsuite/ChangeLog PR target/106122 * gcc.target/i386/pr106122.c: New test case. Diff: --- gcc/config/i386/i386.md | 3 ++- gcc/testsuite/gcc.target/i386/pr106122.c | 15 +++++++++++++++ 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index c74edd1aaef..7c9560fc4f0 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -2519,7 +2519,8 @@ "optimize_insn_for_size_p () && optimize_size > 1 && operands[1] != const0_rtx && IN_RANGE (INTVAL (operands[1]), -128, 127) - && !ix86_red_zone_used" + && !ix86_red_zone_used + && REGNO (operands[0]) != SP_REG" [(set (match_dup 2) (match_dup 1)) (set (match_dup 0) (match_dup 3))] { diff --git a/gcc/testsuite/gcc.target/i386/pr106122.c b/gcc/testsuite/gcc.target/i386/pr106122.c new file mode 100644 index 00000000000..7d24ed3376d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr106122.c @@ -0,0 +1,15 @@ +/* PR middle-end/106122 */ +/* { dg-do compile } */ +/* { dg-options "-Oz" } */ + +register volatile int a __asm__("%esp"); +void foo (void *); +void bar (void *); + +void +baz (void) +{ + foo (__builtin_return_address (0)); + a = 0; + bar (__builtin_return_address (0)); +}