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From: Tobias Burnus <burnus@gcc.gnu.org>
To: gcc-cvs@gcc.gnu.org
Subject: [gcc/devel/omp/gcc-12] amdgcn: remove obsolete assembler workarounds
Date: Tue, 5 Jul 2022 10:32:19 +0000 (GMT) [thread overview]
Message-ID: <20220705103219.5BB4D3856DD4@sourceware.org> (raw)
https://gcc.gnu.org/g:5aeba44d1974fde2f28718715bb3287b7792c03f
commit 5aeba44d1974fde2f28718715bb3287b7792c03f
Author: Andrew Stubbs <ams@codesourcery.com>
Date: Tue Jul 5 11:28:54 2022 +0200
amdgcn: remove obsolete assembler workarounds
This nonsense is no longer required, now that the minimum supported
assembler version is LLVM 13.0.1.
gcc/ChangeLog:
* config/gcn/gcn.md (*movbi): Remove assembler bug workarounds.
(jump): Likewise.
(movdi_symbol_save_scc): Likewise.
(cherry picked from commit b06a282921c71bbc5cab69bc515804bd80f55e92)
Diff:
---
gcc/ChangeLog.omp | 9 +++++++++
gcc/config/gcn/gcn.md | 36 +++++++-----------------------------
2 files changed, 16 insertions(+), 29 deletions(-)
diff --git a/gcc/ChangeLog.omp b/gcc/ChangeLog.omp
index 5fe141fb79a..9d966df94ca 100644
--- a/gcc/ChangeLog.omp
+++ b/gcc/ChangeLog.omp
@@ -1,3 +1,12 @@
+2022-07-05 Tobias Burnus <tobias@codesourcery.com>
+
+ Backport from mainline:
+ 2022-06-27 Andrew Stubbs <ams@codesourcery.com>
+
+ * config/gcn/gcn.md (*movbi): Remove assembler bug workarounds.
+ (jump): Likewise.
+ (movdi_symbol_save_scc): Likewise.
+
2022-07-05 Tobias Burnus <tobias@codesourcery.com>
Backport from mainline:
diff --git a/gcc/config/gcn/gcn.md b/gcc/config/gcn/gcn.md
index 47417ab371e..0f9381c9194 100644
--- a/gcc/config/gcn/gcn.md
+++ b/gcc/config/gcn/gcn.md
@@ -488,14 +488,7 @@
we emit bytes directly as a workaround. */
switch (which_alternative) {
case 0:
- if (REG_P (operands[1]) && REGNO (operands[1]) == SCC_REG)
- return "; s_mov_b32\t%0,%1 is not supported by the assembler.\;"
- ".byte\t0xfd\;"
- ".byte\t0x0\;"
- ".byte\t0x80|%R0\;"
- ".byte\t0xbe";
- else
- return "s_mov_b32\t%0, %1";
+ return "s_mov_b32\t%0, %1";
case 1:
if (REG_P (operands[1]) && REGNO (operands[1]) == SCC_REG)
return "; v_mov_b32\t%0, %1\;"
@@ -512,16 +505,8 @@
case 4:
return "v_cmp_ne_u32\tvcc, 0, %1";
case 5:
- if (REGNO (operands[1]) == SCC_REG)
- return "; s_mov_b32\t%0, %1 is not supported by the assembler.\;"
- ".byte\t0xfd\;"
- ".byte\t0x0\;"
- ".byte\t0xea\;"
- ".byte\t0xbe\;"
- "s_mov_b32\tvcc_hi, 0";
- else
- return "s_mov_b32\tvcc_lo, %1\;"
- "s_mov_b32\tvcc_hi, 0";
+ return "s_mov_b32\tvcc_lo, %1\;"
+ "s_mov_b32\tvcc_hi, 0";
case 6:
case 7:
return "s_load_dword\t%0, %A1\;s_waitcnt\tlgkmcnt(0)";
@@ -768,8 +753,7 @@
return "s_branch\t%0";
else
/* !!! This sequence clobbers EXEC_SAVE_REG and CC_SAVE_REG. */
- return "; s_mov_b32\ts22, scc is not supported by the assembler.\;"
- ".long\t0xbe9600fd\;"
+ return "s_mov_b32\ts22, scc\;"
"s_getpc_b64\ts[20:21]\;"
"s_add_u32\ts20, s20, %0@rel32@lo+4\;"
"s_addc_u32\ts21, s21, %0@rel32@hi+4\;"
@@ -830,11 +814,7 @@
}
else
return "s_cbranch%c1\t.Lskip%=\;"
- "; s_mov_b32\ts22, scc is not supported by the assembler.\;"
- ".byte\t0xfd\;"
- ".byte\t0x0\;"
- ".byte\t0x80|22\;"
- ".byte\t0xbe\;"
+ "s_mov_b32\ts22, scc\;"
"s_getpc_b64\ts[20:21]\;"
"s_add_u32\ts20, s20, %0@rel32@lo+4\;"
"s_addc_u32\ts21, s21, %0@rel32@hi+4\;"
@@ -923,8 +903,7 @@
DGPUs are most likely fine. */
if (SYMBOL_REF_P (operands[1])
&& SYMBOL_REF_WEAK (operands[1]))
- return "; s_mov_b32\ts22, scc is not supported by the assembler.\;"
- ".long\t0xbe9600fd\;"
+ return "s_mov_b32\ts22, scc\;"
"s_getpc_b64\t%0\;"
"s_add_u32\t%L0, %L0, %1@gotpcrel32@lo+4\;"
"s_addc_u32\t%H0, %H0, %1@gotpcrel32@hi+4\;"
@@ -932,8 +911,7 @@
"s_cmpk_lg_u32\ts22, 0\;"
"s_waitcnt\tlgkmcnt(0)";
- return "; s_mov_b32\ts22, scc is not supported by the assembler.\;"
- ".long\t0xbe9600fd\;"
+ return "s_mov_b32\ts22, scc\;"
"s_getpc_b64\t%0\;"
"s_add_u32\t%L0, %L0, %1@rel32@lo+4\;"
"s_addc_u32\t%H0, %H0, %1@rel32@hi+4\;"
reply other threads:[~2022-07-05 10:32 UTC|newest]
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