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From: Roger Sayle <sayle@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-1509] Doubleword version of and; cmp to not; test optimization on x86. Date: Tue, 5 Jul 2022 17:08:38 +0000 (GMT) [thread overview] Message-ID: <20220705170838.3DA823858C2F@sourceware.org> (raw) https://gcc.gnu.org/g:c73e8d45ca0111f51d7187641963df97f5c9c63f commit r13-1509-gc73e8d45ca0111f51d7187641963df97f5c9c63f Author: Roger Sayle <roger@nextmovesoftware.com> Date: Tue Jul 5 18:06:13 2022 +0100 Doubleword version of and;cmp to not;test optimization on x86. This patch extends the earlier and;cmp to not;test optimization to also perform this transformation for TImode on TARGET_64BIT and DImode on -m32, One motivation for this is that it's a step to fixing the current failure of gcc.target/i386/pr65105-5.c on -m32. A more direct benefit for x86_64 is that the following code: int foo(__int128 x, __int128 y) { return (x & y) == y; } improves with -O2 from 15 instructions: movq %rdi, %r8 movq %rsi, %rax movq %rax, %rdi movq %r8, %rsi movq %rdx, %r8 andq %rdx, %rsi andq %rcx, %rdi movq %rsi, %rax movq %rdi, %rdx xorq %r8, %rax xorq %rcx, %rdx orq %rdx, %rax sete %al movzbl %al, %eax ret to the slightly better 13 instructions: movq %rdi, %r8 movq %rsi, %rax movq %r8, %rsi movq %rax, %rdi notq %rsi notq %rdi andq %rdx, %rsi andq %rcx, %rdi movq %rsi, %rax orq %rdi, %rax sete %al movzbl %al, %eax ret 2022-07-05 Roger Sayle <roger@nextmovesoftware.com> gcc/ChangeLog * config/i386/i386.cc (ix86_rtx_costs) <COMPARE>: Provide costs for double word comparisons and tests (comparisons against zero). * config/i386/i386.md (*test<mode>_not_doubleword): Split DWI and;cmp into andn;cmp $0 as a pre-reload splitter. (*andn<dwi>3_doubleword_bmi): Use <dwi> instead of <mode> in name. (*<any_or><dwi>3_doubleword): Likewise. gcc/testsuite/ChangeLog * gcc.target/i386/testnot-3.c: New test case. Diff: --- gcc/config/i386/i386.cc | 13 +++++++++++++ gcc/config/i386/i386.md | 22 ++++++++++++++++++++-- gcc/testsuite/gcc.target/i386/testnot-3.c | 9 +++++++++ 3 files changed, 42 insertions(+), 2 deletions(-) diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc index 0cfe9962f75..95cb1e2ce70 100644 --- a/gcc/config/i386/i386.cc +++ b/gcc/config/i386/i386.cc @@ -20982,6 +20982,19 @@ ix86_rtx_costs (rtx x, machine_mode mode, int outer_code_i, int opno, return true; } + if (SCALAR_INT_MODE_P (GET_MODE (op0)) + && GET_MODE_SIZE (GET_MODE (op0)) > UNITS_PER_WORD) + { + if (op1 == const0_rtx) + *total = cost->add + + rtx_cost (op0, GET_MODE (op0), outer_code, opno, speed); + else + *total = 3*cost->add + + rtx_cost (op0, GET_MODE (op0), outer_code, opno, speed) + + rtx_cost (op1, GET_MODE (op0), outer_code, opno, speed); + return true; + } + /* The embedded comparison operand is completely free. */ if (!general_operand (op0, GET_MODE (op0)) && op1 == const0_rtx) *total = 0; diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index d11475489fc..bdde577ddb5 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -9792,7 +9792,25 @@ (set (reg:CCZ FLAGS_REG) (compare:CCZ (and:SWI (match_dup 2) (match_dup 1)) (const_int 0)))] + "operands[2] = gen_reg_rtx (<MODE>mode);") + +;; Split and;cmp (as optimized by combine) into andn;cmp $0 +(define_insn_and_split "*test<mode>_not_doubleword" + [(set (reg:CCZ FLAGS_REG) + (compare:CCZ + (and:DWI + (not:DWI (match_operand:DWI 0 "nonimmediate_operand")) + (match_operand:DWI 1 "nonimmediate_operand")) + (const_int 0)))] + "ix86_pre_reload_split ()" + "#" + "&& 1" + [(parallel + [(set (match_dup 2) (and:DWI (not:DWI (match_dup 0)) (match_dup 1))) + (clobber (reg:CC FLAGS_REG))]) + (set (reg:CCZ FLAGS_REG) (compare:CCZ (match_dup 2) (const_int 0)))] { + operands[0] = force_reg (<MODE>mode, operands[0]); operands[2] = gen_reg_rtx (<MODE>mode); }) @@ -10404,7 +10422,7 @@ operands[2] = gen_int_mode (INTVAL (operands[2]), QImode); }) -(define_insn_and_split "*andn<mode>3_doubleword_bmi" +(define_insn_and_split "*andn<dwi>3_doubleword_bmi" [(set (match_operand:<DWI> 0 "register_operand" "=r") (and:<DWI> (not:<DWI> (match_operand:<DWI> 1 "register_operand" "r")) @@ -10618,7 +10636,7 @@ DONE; }) -(define_insn_and_split "*<code><mode>3_doubleword" +(define_insn_and_split "*<code><dwi>3_doubleword" [(set (match_operand:<DWI> 0 "nonimmediate_operand" "=ro,r") (any_or:<DWI> (match_operand:<DWI> 1 "nonimmediate_operand" "%0,0") diff --git a/gcc/testsuite/gcc.target/i386/testnot-3.c b/gcc/testsuite/gcc.target/i386/testnot-3.c new file mode 100644 index 00000000000..7c54dbc3421 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/testnot-3.c @@ -0,0 +1,9 @@ +/* { dg-do compile { target int128 } } */ +/* { dg-options "-O2" } */ + +int foo(__int128 x, __int128 y) +{ + return (x & y) == y; +} + +/* { dg-final { scan-assembler-not "xorq" } } */
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