From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 401AD3857B89; Thu, 7 Jul 2022 20:14:05 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 401AD3857B89 Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work093)] Revert patch. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work093 X-Git-Oldrev: 7362063408a52f997db8a130af9b97aad5a92a75 X-Git-Newrev: 8bab85c05eea92fe644832c450de113879206bd9 Message-Id: <20220707201405.401AD3857B89@sourceware.org> Date: Thu, 7 Jul 2022 20:14:05 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Jul 2022 20:14:05 -0000 https://gcc.gnu.org/g:8bab85c05eea92fe644832c450de113879206bd9 commit 8bab85c05eea92fe644832c450de113879206bd9 Author: Michael Meissner Date: Thu Jul 7 16:13:02 2022 -0400 Revert patch. 2022-07-07 Michael Meissner gcc/ Revert patch. * config/rs6000/predicate.md (kf_or_tf_operand): New predicate. * config/rs6000/rs6000.md (add3_odd): Use kf_or_tf_operand instead of altivec_register_operand. (sub3_odd): Likewise. (mul3_odd): Likewise. (div3_odd): Likewise. (sqrt2_odd): Likewise. (fma4_odd): Likewise. (fms4_odd): Likewise. (nfma4_odd): Likewise. (nfms4_odd): Likewise. * config/rs6000/vsx.md (xsxexpqp_): Likewise. (xsxsigqp_): Likewise. (xsiexpqpf_): Likewise. (xscmpexpqp__): Likewise. (xscmpexpqp__): Likewise. (xststdcqp_): Likewise. (xststdcnegqp_): Likewise. (xststdcqp_): Likewise. 2022-07-07 Michael Meissner gcc/ Revert patch. * config/rs6000/rs6000-builtin.cc (rs6000_expand_builtin): If we have certain KFmode built-in functions, convert to TFmode if a long double was passed, and long double is IEEE 128-bit. Also if the modes are different, call convert_to_mode instead of copy_to_mode_reg. 2022-07-07 Michael Meissner gcc/ * ChangeLog.meissner: Update. Diff: --- gcc/ChangeLog.meissner | 42 ++--------------------- gcc/config/rs6000/predicates.md | 26 -------------- gcc/config/rs6000/rs6000-builtin.cc | 68 +------------------------------------ gcc/config/rs6000/rs6000.md | 42 +++++++++++------------ gcc/config/rs6000/vsx.md | 20 +++++------ 5 files changed, 34 insertions(+), 164 deletions(-) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index d2fd8420538..edfbf0c47d9 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -1,44 +1,6 @@ -==================== work093, patch #9 +==================== work093, patch #9 (reverted) -Allow KF/TF conversions in IEEE 128-bit insns. - -2022-07-07 Michael Meissner - -gcc/ - - * config/rs6000/predicate.md (kf_or_tf_operand): New predicate. - * config/rs6000/rs6000.md (add3_odd): Use kf_or_tf_operand - instead of altivec_register_operand. - (sub3_odd): Likewise. - (mul3_odd): Likewise. - (div3_odd): Likewise. - (sqrt2_odd): Likewise. - (fma4_odd): Likewise. - (fms4_odd): Likewise. - (nfma4_odd): Likewise. - (nfms4_odd): Likewise. - * config/rs6000/vsx.md (xsxexpqp_): Likewise. - (xsxsigqp_): Likewise. - (xsiexpqpf_): Likewise. - (xscmpexpqp__): Likewise. - (xscmpexpqp__): Likewise. - (xststdcqp_): Likewise. - (xststdcnegqp_): Likewise. - (xststdcqp_): Likewise. - -==================== work093, patch #8 - -Fixup KFmode to TFmode built-in functions. - -2022-07-07 Michael Meissner - -gcc/ - - * config/rs6000/rs6000-builtin.cc (rs6000_expand_builtin): If we - have certain KFmode built-in functions, convert to TFmode if a - long double was passed, and long double is IEEE 128-bit. Also if - the modes are different, call convert_to_mode instead of - copy_to_mode_reg. +==================== work093, patch #8 (reverted) ==================== work093, patch #7 diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index 873dbbb22f9..b1fcc69bb60 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -2064,29 +2064,3 @@ else return false; }) - -;; Return 1 if the argument is KFmode or TFmode (when TFmode is IEEE 128-bit). -;; Include various conversions between these formats. This allows passing long -;; double to IEEE 128-bit built-ins without separate conversions. -;; -;; Since all of the instructions that operate on IEEE 128-bit require Altivec -;; registers, check that the register is an Altivec register. -(define_predicate "kf_or_tf_operand" - (match_code "reg,subreg,float_extend,float_truncate") -{ - if (mode == VOIDmode) - mode = GET_MODE (op); - - if (!FLOAT128_IEEE_P (mode)) - return 0; - - if (GET_CODE (op) == FLOAT_EXTEND || GET_CODE (op) == FLOAT_TRUNCATE) - { - op = XEXP (op, 0); - mode = GET_MODE (op); - if (!FLOAT128_IEEE_P (mode)) - return 0; - } - - return altivec_register_operand (op, mode); -}) diff --git a/gcc/config/rs6000/rs6000-builtin.cc b/gcc/config/rs6000/rs6000-builtin.cc index 64e3a375dd5..457e463087f 100644 --- a/gcc/config/rs6000/rs6000-builtin.cc +++ b/gcc/config/rs6000/rs6000-builtin.cc @@ -3290,70 +3290,6 @@ rs6000_expand_builtin (tree exp, rtx target, rtx /* subtarget */, size_t uns_fcode = (size_t)fcode; enum insn_code icode = rs6000_builtin_info[uns_fcode].icode; - /* If long double is IEEE 128-bit, we may need to convert from the KFmode - builtin function to the TFmode builtin function if the argument is long - double (i.e. TFmode). */ - if (FLOAT128_IEEE_P (TFmode) && call_expr_nargs (exp) >= 1) - { - if (TYPE_MODE (TREE_TYPE (CALL_EXPR_ARG (exp, 0))) == TFmode) - switch (icode) - { - case CODE_FOR_sqrtkf2_odd: - icode = CODE_FOR_sqrttf2_odd; - break; - case CODE_FOR_trunckfdf2_odd: - icode = CODE_FOR_trunctfdf2_odd; - break; - case CODE_FOR_addkf3_odd: - icode = CODE_FOR_addtf3_odd; - break; - case CODE_FOR_subkf3_odd: - icode = CODE_FOR_subtf3_odd; - break; - case CODE_FOR_mulkf3_odd: - icode = CODE_FOR_multf3_odd; - break; - case CODE_FOR_divkf3_odd: - icode = CODE_FOR_divtf3_odd; - break; - case CODE_FOR_fmakf4_odd: - icode = CODE_FOR_fmatf4_odd; - break; - case CODE_FOR_xsxexpqp_kf: - icode = CODE_FOR_xsxexpqp_tf; - break; - case CODE_FOR_xsxsigqp_kf: - icode = CODE_FOR_xsxsigqp_tf; - break; - case CODE_FOR_xststdcnegqp_kf: - icode = CODE_FOR_xststdcnegqp_tf; - break; - case CODE_FOR_xsiexpqp_kf: - icode = CODE_FOR_xsiexpqp_tf; - break; - case CODE_FOR_xsiexpqpf_kf: - icode = CODE_FOR_xsiexpqpf_tf; - break; - case CODE_FOR_xststdcqp_kf: - icode = CODE_FOR_xststdcqp_tf; - break; - case CODE_FOR_xscmpexpqp_eq_kf: - icode = CODE_FOR_xscmpexpqp_eq_tf; - break; - case CODE_FOR_xscmpexpqp_lt_kf: - icode = CODE_FOR_xscmpexpqp_lt_tf; - break; - case CODE_FOR_xscmpexpqp_gt_kf: - icode = CODE_FOR_xscmpexpqp_gt_tf; - break; - case CODE_FOR_xscmpexpqp_unordered_kf: - icode = CODE_FOR_xscmpexpqp_unordered_tf; - break; - default: - break; - } - } - /* In case of "#pragma target" changes, we initialize all builtins but check for actual availability now, during expand time. For invalid builtins, generate a normal call. */ @@ -3655,9 +3591,7 @@ rs6000_expand_builtin (tree exp, rtx target, rtx /* subtarget */, for (int i = 0; i < nargs; i++) if (!insn_data[icode].operand[i+k].predicate (op[i], mode[i+k])) - op[i] = ((mode[i+k] == GET_MODE (op[i]) || GET_MODE (op[i]) == VOIDmode) - ? copy_to_mode_reg (mode[i+k], op[i]) - : convert_to_mode (mode[i+k], op[i], false)); + op[i] = copy_to_mode_reg (mode[i+k], op[i]); rtx pat; diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index e70438b519b..ec39358ebe8 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -15180,8 +15180,8 @@ (define_insn "add3_odd" [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") (unspec:IEEE128 - [(match_operand:IEEE128 1 "kf_or_tf_operand" "v") - (match_operand:IEEE128 2 "kf_or_tf_operand" "v")] + [(match_operand:IEEE128 1 "altivec_register_operand" "v") + (match_operand:IEEE128 2 "altivec_register_operand" "v")] UNSPEC_ADD_ROUND_TO_ODD))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" "xsaddqpo %0,%1,%2" @@ -15191,8 +15191,8 @@ (define_insn "sub3_odd" [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") (unspec:IEEE128 - [(match_operand:IEEE128 1 "kf_or_tf_operand" "v") - (match_operand:IEEE128 2 "kf_or_tf_operand" "v")] + [(match_operand:IEEE128 1 "altivec_register_operand" "v") + (match_operand:IEEE128 2 "altivec_register_operand" "v")] UNSPEC_SUB_ROUND_TO_ODD))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" "xssubqpo %0,%1,%2" @@ -15202,8 +15202,8 @@ (define_insn "mul3_odd" [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") (unspec:IEEE128 - [(match_operand:IEEE128 1 "kf_or_tf_operand" "v") - (match_operand:IEEE128 2 "kf_or_tf_operand" "v")] + [(match_operand:IEEE128 1 "altivec_register_operand" "v") + (match_operand:IEEE128 2 "altivec_register_operand" "v")] UNSPEC_MUL_ROUND_TO_ODD))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" "xsmulqpo %0,%1,%2" @@ -15213,8 +15213,8 @@ (define_insn "div3_odd" [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") (unspec:IEEE128 - [(match_operand:IEEE128 1 "kf_or_tf_operand" "v") - (match_operand:IEEE128 2 "kf_or_tf_operand" "v")] + [(match_operand:IEEE128 1 "altivec_register_operand" "v") + (match_operand:IEEE128 2 "altivec_register_operand" "v")] UNSPEC_DIV_ROUND_TO_ODD))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" "xsdivqpo %0,%1,%2" @@ -15224,7 +15224,7 @@ (define_insn "sqrt2_odd" [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") (unspec:IEEE128 - [(match_operand:IEEE128 1 "kf_or_tf_operand" "v")] + [(match_operand:IEEE128 1 "altivec_register_operand" "v")] UNSPEC_SQRT_ROUND_TO_ODD))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" "xssqrtqpo %0,%1" @@ -15234,9 +15234,9 @@ (define_insn "fma4_odd" [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") (unspec:IEEE128 - [(match_operand:IEEE128 1 "kf_or_tf_operand" "v") - (match_operand:IEEE128 2 "kf_or_tf_operand" "v") - (match_operand:IEEE128 3 "kf_or_tf_operand" "0")] + [(match_operand:IEEE128 1 "altivec_register_operand" "v") + (match_operand:IEEE128 2 "altivec_register_operand" "v") + (match_operand:IEEE128 3 "altivec_register_operand" "0")] UNSPEC_FMA_ROUND_TO_ODD))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" "xsmaddqpo %0,%1,%2" @@ -15246,10 +15246,10 @@ (define_insn "*fms4_odd" [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") (unspec:IEEE128 - [(match_operand:IEEE128 1 "kf_or_tf_operand" "%v") - (match_operand:IEEE128 2 "kf_or_tf_operand" "v") + [(match_operand:IEEE128 1 "altivec_register_operand" "%v") + (match_operand:IEEE128 2 "altivec_register_operand" "v") (neg:IEEE128 - (match_operand:IEEE128 3 "kf_or_tf_operand" "0"))] + (match_operand:IEEE128 3 "altivec_register_operand" "0"))] UNSPEC_FMA_ROUND_TO_ODD))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" "xsmsubqpo %0,%1,%2" @@ -15260,9 +15260,9 @@ [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") (neg:IEEE128 (unspec:IEEE128 - [(match_operand:IEEE128 1 "kf_or_tf_operand" "%v") - (match_operand:IEEE128 2 "kf_or_tf_operand" "v") - (match_operand:IEEE128 3 "kf_or_tf_operand" "0")] + [(match_operand:IEEE128 1 "altivec_register_operand" "%v") + (match_operand:IEEE128 2 "altivec_register_operand" "v") + (match_operand:IEEE128 3 "altivec_register_operand" "0")] UNSPEC_FMA_ROUND_TO_ODD)))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" "xsnmaddqpo %0,%1,%2" @@ -15273,10 +15273,10 @@ [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") (neg:IEEE128 (unspec:IEEE128 - [(match_operand:IEEE128 1 "kf_or_tf_operand" "%v") - (match_operand:IEEE128 2 "kf_or_tf_operand" "v") + [(match_operand:IEEE128 1 "altivec_register_operand" "%v") + (match_operand:IEEE128 2 "altivec_register_operand" "v") (neg:IEEE128 - (match_operand:IEEE128 3 "kf_or_tf_operand" "0"))] + (match_operand:IEEE128 3 "altivec_register_operand" "0"))] UNSPEC_FMA_ROUND_TO_ODD)))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" "xsnmsubqpo %0,%1,%2" diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 87efdaa1756..e226a93bbe5 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -5087,7 +5087,7 @@ ;; VSX Scalar Extract Exponent Quad-Precision (define_insn "xsxexpqp_" [(set (match_operand:DI 0 "altivec_register_operand" "=v") - (unspec:DI [(match_operand:IEEE128 1 "kf_or_tf_operand" "v")] + (unspec:DI [(match_operand:IEEE128 1 "altivec_register_operand" "v")] UNSPEC_VSX_SXEXPDP))] "TARGET_P9_VECTOR" "xsxexpqp %0,%1" @@ -5105,7 +5105,7 @@ ;; VSX Scalar Extract Significand Quad-Precision (define_insn "xsxsigqp_" [(set (match_operand:TI 0 "altivec_register_operand" "=v") - (unspec:TI [(match_operand:IEEE128 1 "kf_or_tf_operand" "v")] + (unspec:TI [(match_operand:IEEE128 1 "altivec_register_operand" "v")] UNSPEC_VSX_SXSIG))] "TARGET_P9_VECTOR" "xsxsigqp %0,%1" @@ -5124,7 +5124,7 @@ (define_insn "xsiexpqpf_" [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") (unspec:IEEE128 - [(match_operand:IEEE128 1 "kf_or_tf_operand" "v") + [(match_operand:IEEE128 1 "altivec_register_operand" "v") (match_operand:DI 2 "altivec_register_operand" "v")] UNSPEC_VSX_SIEXPQP))] "TARGET_P9_VECTOR" @@ -5200,8 +5200,8 @@ [(set (match_dup 3) (compare:CCFP (unspec:IEEE128 - [(match_operand:IEEE128 1 "kf_or_tf_operand" "v") - (match_operand:IEEE128 2 "kf_or_tf_operand" "v")] + [(match_operand:IEEE128 1 "vsx_register_operand" "v") + (match_operand:IEEE128 2 "vsx_register_operand" "v")] UNSPEC_VSX_SCMPEXPQP) (const_int 0))) (set (match_operand:SI 0 "register_operand" "=r") @@ -5221,8 +5221,8 @@ (define_insn "*xscmpexpqp" [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") (compare:CCFP - (unspec:IEEE128 [(match_operand:IEEE128 1 "kf_or_tf_operand" "v") - (match_operand:IEEE128 2 "kf_or_tf_operand" "v")] + (unspec:IEEE128 [(match_operand:IEEE128 1 "altivec_register_operand" "v") + (match_operand:IEEE128 2 "altivec_register_operand" "v")] UNSPEC_VSX_SCMPEXPQP) (match_operand:SI 3 "zero_constant" "j")))] "TARGET_P9_VECTOR" @@ -5238,7 +5238,7 @@ [(set (match_dup 3) (compare:CCFP (unspec:IEEE128 - [(match_operand:IEEE128 1 "kf_or_tf_operand" "v") + [(match_operand:IEEE128 1 "altivec_register_operand" "v") (match_operand:SI 2 "u7bit_cint_operand" "n")] UNSPEC_VSX_STSTDC) (const_int 0))) @@ -5276,7 +5276,7 @@ [(set (match_dup 2) (compare:CCFP (unspec:IEEE128 - [(match_operand:IEEE128 1 "kf_or_tf_operand" "v") + [(match_operand:IEEE128 1 "altivec_register_operand" "v") (const_int 0)] UNSPEC_VSX_STSTDC) (const_int 0))) @@ -5310,7 +5310,7 @@ [(set (match_operand:CCFP 0 "" "=y") (compare:CCFP (unspec:IEEE128 - [(match_operand:IEEE128 1 "kf_or_tf_operand" "v") + [(match_operand:IEEE128 1 "altivec_register_operand" "v") (match_operand:SI 2 "u7bit_cint_operand" "n")] UNSPEC_VSX_STSTDC) (const_int 0)))]