From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 7856) id 951C6385C329; Sun, 10 Jul 2022 03:40:49 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 951C6385C329 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Xi Ruoyao To: gcc-cvs@gcc.gnu.org Subject: [gcc r12-8562] loongarch: fix mulsidi3_64bit instruction X-Act-Checkin: gcc X-Git-Author: Xi Ruoyao X-Git-Refname: refs/heads/releases/gcc-12 X-Git-Oldrev: 7282722666c2bc43a4f10dcb88b100f8fe4d7bcc X-Git-Newrev: b568e0db565b189eb434dbd44791aa816d71e72f Message-Id: <20220710034049.951C6385C329@sourceware.org> Date: Sun, 10 Jul 2022 03:40:49 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 10 Jul 2022 03:40:49 -0000 https://gcc.gnu.org/g:b568e0db565b189eb434dbd44791aa816d71e72f commit r12-8562-gb568e0db565b189eb434dbd44791aa816d71e72f Author: Xi Ruoyao Date: Fri Jul 8 21:09:25 2022 +0800 loongarch: fix mulsidi3_64bit instruction (mult (sign_extend:DI rj:SI) (sign_extend:DI rk:SI)) should be "mulw.d.w", not "mul.d". gcc/ChangeLog: * config/loongarch/loongarch.md (mulsidi3_64bit): Use mulw.d.w instead of mul.d. gcc/testsuite/ChangeLog: * gcc.target/loongarch/mulw_d_w.c: New test. * gcc.c-torture/execute/mul-sext.c: New test. (cherry picked from commit 1fa42d62140b56589771eb3d46f89c810bfc8e0a) Diff: --- gcc/config/loongarch/loongarch.md | 2 +- gcc/testsuite/gcc.c-torture/execute/mul-sext.c | 20 ++++++++++++++++++++ gcc/testsuite/gcc.target/loongarch/mulw_d_w.c | 10 ++++++++++ 3 files changed, 31 insertions(+), 1 deletion(-) diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index d3c809e25f3..8f8412fba84 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -621,7 +621,7 @@ (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r")) (sign_extend:DI (match_operand:SI 2 "register_operand" "r"))))] "TARGET_64BIT" - "mul.d\t%0,%1,%2" + "mulw.d.w\t%0,%1,%2" [(set_attr "type" "imul") (set_attr "mode" "DI")]) diff --git a/gcc/testsuite/gcc.c-torture/execute/mul-sext.c b/gcc/testsuite/gcc.c-torture/execute/mul-sext.c new file mode 100644 index 00000000000..8b6800804fb --- /dev/null +++ b/gcc/testsuite/gcc.c-torture/execute/mul-sext.c @@ -0,0 +1,20 @@ +/* { dg-do run } */ + +typedef __INT64_TYPE__ int64_t; +typedef __INT32_TYPE__ int32_t; + +/* f() was misoptimized to a single "mul.d" instruction on LA64. */ +__attribute__((noipa, noinline)) int64_t +f(int64_t a, int64_t b) +{ + return (int64_t)(int32_t)a * (int64_t)(int32_t)b; +} + +int +main() +{ + int64_t a = 0x1145140000000001; + int64_t b = 0x1919810000000001; + if (f(a, b) != 1) + __builtin_abort(); +} diff --git a/gcc/testsuite/gcc.target/loongarch/mulw_d_w.c b/gcc/testsuite/gcc.target/loongarch/mulw_d_w.c new file mode 100644 index 00000000000..4ab7df8836b --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/mulw_d_w.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mabi=lp64d" } */ +/* { dg-final { scan-assembler "mulw.d.w" } } */ + +/* This should be optimized to mulw.d.w for LA64. */ +__attribute__((noipa, noinline)) long +f(long a, long b) +{ + return (long)(int)a * (long)(int)b; +}