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From: Michael Meissner <meissner@gcc.gnu.org>
To: gcc-cvs@gcc.gnu.org
Subject: [gcc(refs/users/meissner/heads/work093)] Make __ibm128 support work on older machines.
Date: Tue, 12 Jul 2022 01:36:13 +0000 (GMT) [thread overview]
Message-ID: <20220712013613.2C974382FDCA@sourceware.org> (raw)
https://gcc.gnu.org/g:3fa02c40fc3bc917edeff0c0dcb0e91ae7f5abfb
commit 3fa02c40fc3bc917edeff0c0dcb0e91ae7f5abfb
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Mon Jul 11 21:35:53 2022 -0400
Make __ibm128 support work on older machines.
2022-07-08 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/rs600.md (IFKF): Delete.
(IFKF_reg): Delete.
(extendiftf2): Allow __ibm128 on older systems.
(extendtfif2): Likewise.
(trunciftf2): Likewise.
(trunctfif2): Likewise.
(extendkftf2_internal): Split extend<mode>tf2_internal and
extendtf<mode>2_internal into separate insns that handle either
conversions between IEEE 128-bit types or between IBM 128-bit
types. Set the type and insn length correctly.
(extendtfkf2_internal): Likewise.
(extendiftf2_internal): Likewise.
(extendtfif2_internal): Likewise.
Diff:
---
gcc/config/rs6000/rs6000.md | 84 ++++++++++++++++++++++++++++++++-------------
1 file changed, 60 insertions(+), 24 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index ec39358ebe8..08165822be5 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -543,12 +543,6 @@
; Iterator for 128-bit VSX types for pack/unpack
(define_mode_iterator FMOVE128_VSX [V1TI KF])
-; Iterators for converting to/from TFmode
-(define_mode_iterator IFKF [IF KF])
-
-; Constraints for moving IF/KFmode.
-(define_mode_attr IFKF_reg [(IF "d") (KF "wa")])
-
; Whether a floating point move is ok, don't allow SD without hardware FP
(define_mode_attr fmove_ok [(SF "")
(DF "")
@@ -9061,7 +9055,7 @@
(define_expand "extendiftf2"
[(set (match_operand:TF 0 "gpc_reg_operand")
(float_extend:TF (match_operand:IF 1 "gpc_reg_operand")))]
- "TARGET_FLOAT128_TYPE"
+ "TARGET_FLOAT128_TYPE || TARGET_LONG_DOUBLE_128"
{
rs6000_expand_float128_convert (operands[0], operands[1], false);
DONE;
@@ -9097,7 +9091,7 @@
(define_expand "extendtfif2"
[(set (match_operand:IF 0 "gpc_reg_operand")
(float_extend:IF (match_operand:TF 1 "gpc_reg_operand")))]
- "TARGET_FLOAT128_TYPE"
+ "TARGET_FLOAT128_TYPE || TARGET_LONG_DOUBLE_128"
{
rs6000_expand_float128_convert (operands[0], operands[1], false);
DONE;
@@ -9106,7 +9100,7 @@
(define_expand "trunciftf2"
[(set (match_operand:TF 0 "gpc_reg_operand")
(float_truncate:TF (match_operand:IF 1 "gpc_reg_operand")))]
- "TARGET_FLOAT128_TYPE"
+ "TARGET_FLOAT128_TYPE || TARGET_LONG_DOUBLE_128"
{
rs6000_expand_float128_convert (operands[0], operands[1], false);
DONE;
@@ -9142,37 +9136,79 @@
(define_expand "trunctfif2"
[(set (match_operand:IF 0 "gpc_reg_operand")
(float_truncate:IF (match_operand:TF 1 "gpc_reg_operand")))]
- "TARGET_FLOAT128_TYPE"
+ "TARGET_FLOAT128_TYPE || TARGET_LONG_DOUBLE_128"
{
rs6000_expand_float128_convert (operands[0], operands[1], false);
DONE;
})
-(define_insn_and_split "*extend<mode>tf2_internal"
- [(set (match_operand:TF 0 "gpc_reg_operand" "=<IFKF_reg>")
+;; Convert between KFmode and TFmode when -mabi=ieeelongdouble
+(define_insn_and_split "*extendkftf2_internal"
+ [(set (match_operand:TF 0 "gpc_reg_operand" "=wa,wa")
(float_extend:TF
- (match_operand:IFKF 1 "gpc_reg_operand" "<IFKF_reg>")))]
- "TARGET_FLOAT128_TYPE
- && FLOAT128_IBM_P (TFmode) == FLOAT128_IBM_P (<MODE>mode)"
+ (match_operand:KF 1 "gpc_reg_operand" "0,wa")))]
+ "FLOAT128_IEEE_P (TFmode)"
"#"
"&& reload_completed"
[(set (match_dup 0) (match_dup 2))]
{
operands[2] = gen_rtx_REG (TFmode, REGNO (operands[1]));
-})
+}
+ [(set_attr "type" "vecsimple")])
-(define_insn_and_split "*extendtf<mode>2_internal"
- [(set (match_operand:IFKF 0 "gpc_reg_operand" "=<IFKF_reg>")
- (float_extend:IFKF
- (match_operand:TF 1 "gpc_reg_operand" "<IFKF_reg>")))]
- "TARGET_FLOAT128_TYPE
- && FLOAT128_IBM_P (TFmode) == FLOAT128_IBM_P (<MODE>mode)"
+(define_insn_and_split "*extendtfkf2_internal"
+ [(set (match_operand:KF 0 "gpc_reg_operand" "=wa,wa")
+ (float_extend:KF
+ (match_operand:TF 1 "gpc_reg_operand" "0,wa")))]
+ "FLOAT128_IEEE_P (TFmode)"
"#"
"&& reload_completed"
[(set (match_dup 0) (match_dup 2))]
{
- operands[2] = gen_rtx_REG (<MODE>mode, REGNO (operands[1]));
-})
+ operands[2] = gen_rtx_REG (KFmode, REGNO (operands[1]));
+}
+ [(set_attr "type" "vecsimple")])
+
+;; Convert between IFmode and TFmode when -mabi=ibmlongdouble
+(define_insn_and_split "*extendiftf2_internal"
+ [(set (match_operand:TF 0 "gpc_reg_operand" "=d,&d")
+ (float_extend:TF
+ (match_operand:IF 1 "input_operand" "0,d")))]
+ "FLOAT128_IBM_P (TFmode)"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 2) (match_dup 3))
+ (set (match_dup 4) (match_dup 5))]
+{
+ unsigned int op0_regno = reg_or_subregno (operands[0]);
+ unsigned int op1_regno = reg_or_subregno (operands[1]);
+ operands[2] = gen_rtx_REG (DFmode, op0_regno);
+ operands[3] = gen_rtx_REG (DFmode, op1_regno);
+ operands[4] = gen_rtx_REG (DFmode, op0_regno + 1);
+ operands[5] = gen_rtx_REG (DFmode, op1_regno + 1);
+}
+ [(set_attr "type" "two")
+ (set_attr "num_insns" "2")])
+
+(define_insn_and_split "*extendtfif2_internal"
+ [(set (match_operand:IF 0 "gpc_reg_operand" "=d,&d")
+ (float_extend:IF
+ (match_operand:TF 1 "input_operand" "0,d")))]
+ "FLOAT128_IBM_P (TFmode)"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 2) (match_dup 3))
+ (set (match_dup 4) (match_dup 5))]
+{
+ unsigned int op0_regno = reg_or_subregno (operands[0]);
+ unsigned int op1_regno = reg_or_subregno (operands[1]);
+ operands[2] = gen_rtx_REG (DFmode, op0_regno);
+ operands[3] = gen_rtx_REG (DFmode, op1_regno);
+ operands[4] = gen_rtx_REG (DFmode, op0_regno + 1);
+ operands[5] = gen_rtx_REG (DFmode, op1_regno + 1);
+}
+ [(set_attr "type" "two")
+ (set_attr "num_insns" "2")])
\f
;; Reload helper functions used by rs6000_secondary_reload. The patterns all
reply other threads:[~2022-07-12 1:36 UTC|newest]
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