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From: Stam Markianos-Wright <stammark@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/vendors/ARM/heads/morello)] Fix Hybrid Morello unwinding: dwarf reg sizes and PAC builtins Date: Tue, 12 Jul 2022 10:24:03 +0000 (GMT) [thread overview] Message-ID: <20220712102403.8B0803857434@sourceware.org> (raw) https://gcc.gnu.org/g:6c7481a4f94978351fc26e33f66b1fbe36dc82e5 commit 6c7481a4f94978351fc26e33f66b1fbe36dc82e5 Author: Stam Markianos-Wright <stam.markianos-wright@arm.com> Date: Mon Jul 4 13:06:35 2022 +0100 Fix Hybrid Morello unwinding: dwarf reg sizes and PAC builtins Two GCC codegen issues were found that would lead to unwinding not working in Hybrid Morello: - Firstly, we'd miscompile `init_dwarf_reg_size_table`: This is a strange interaction between `hard_regno_call_part_clobbered` and `reg_raw_mode`. In a previous commit we changed `hard_regno_call_part_clobbered` to return true for CADImode in Hybrid capability compilation for all GP registers, which then made `default_dwarf_frame_reg_mode` fall into using `choose_hard_reg_mode` to select the machine mode. Due to `abi->clobbers_reg_p` having already been set by this point, that would then return VOIDmode, which has a MODE_SIZE of zero, leading to `dwarf_reg_size_table` being initialised with zeroes. The issue here was that this would happen for all GP registers, when really it should only happen for callee-saved registers. - Secondly, we'd miscompile `aarch64_demangle_return_addr`: The PAC builtins used in this functions are disabled for Morello arch and the Purecap ABI, but we've done that by simply returning `target` which may be initialized at this point. Here I simply return the expansion of the 1st argument (the address), instead. Diff: --- gcc/config/aarch64/aarch64-builtins.c | 9 +++++---- gcc/config/aarch64/aarch64.c | 3 ++- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/gcc/config/aarch64/aarch64-builtins.c b/gcc/config/aarch64/aarch64-builtins.c index 23ebbffcbc5..891e821a77f 100644 --- a/gcc/config/aarch64/aarch64-builtins.c +++ b/gcc/config/aarch64/aarch64-builtins.c @@ -2188,10 +2188,6 @@ aarch64_general_expand_builtin (unsigned int fcode, tree exp, rtx target, case AARCH64_PAUTH_BUILTIN_AUTIB1716: case AARCH64_PAUTH_BUILTIN_PACIB1716: case AARCH64_PAUTH_BUILTIN_XPACLRI: - /* PAC + capabilities are not supported: expand the builtins as - no-ops if we're compiling for a capability target. */ - if (TARGET_CAPABILITY_ANY) - return target; arg0 = CALL_EXPR_ARG (exp, 0); op0 = force_reg (Pmode, expand_normal (arg0)); @@ -2203,6 +2199,11 @@ aarch64_general_expand_builtin (unsigned int fcode, tree exp, rtx target, emit_move_insn (target, op0); + /* PAC + capabilities are not supported: expand the builtins as + no-ops if we're compiling for a capability target. */ + if (TARGET_CAPABILITY_ANY) + return target; + if (fcode == AARCH64_PAUTH_BUILTIN_XPACLRI) { rtx lr = gen_rtx_REG (Pmode, R30_REGNUM); diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 1e7ab8ef9ac..15b642c2b7e 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -2879,7 +2879,8 @@ aarch64_hard_regno_call_part_clobbered (unsigned int abi_id, unsigned int regno, machine_mode mode) { - if (TARGET_CAPABILITY_HYBRID && mode == CADImode && GP_REGNUM_P (regno)) + if (TARGET_CAPABILITY_HYBRID && mode == CADImode + && regno >= R19_REGNUM && regno <= R28_REGNUM) return true; if (FP_REGNUM_P (regno) && abi_id != ARM_PCS_SVE)
next reply other threads:[~2022-07-12 10:24 UTC|newest] Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-07-12 10:24 Stam Markianos-Wright [this message] -- strict thread matches above, loose matches on Subject: below -- 2022-07-04 12:06 Stam Markianos-Wright
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