From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 61FA33858284; Mon, 18 Jul 2022 19:41:17 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 61FA33858284 Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work095)] Update ChangeLog.meissner. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work095 X-Git-Oldrev: e5a8dfceb96a3ef5bde9ff7cd352cdf5902b9d32 X-Git-Newrev: 8f3d146c0445dde1aa39bbe536a9bc0a19ab1c85 Message-Id: <20220718194117.61FA33858284@sourceware.org> Date: Mon, 18 Jul 2022 19:41:17 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 18 Jul 2022 19:41:17 -0000 https://gcc.gnu.org/g:8f3d146c0445dde1aa39bbe536a9bc0a19ab1c85 commit 8f3d146c0445dde1aa39bbe536a9bc0a19ab1c85 Author: Michael Meissner Date: Mon Jul 18 15:40:58 2022 -0400 Update ChangeLog.meissner. 2022-07-18 Michael Meissner gcc/ * ChangeLog.meissner: Update. Diff: --- gcc/ChangeLog.meissner | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index 6e19866402e..e8ee95fdc9e 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -1,3 +1,41 @@ +==================== work095, patch #2. + +Remove setting -mblock-ops-vector-pair on power10. + +Testing has shown that using the load vector pair and store vector pair +instructions for block moves has some performance issues on power10. This +patch does not set this option by default. If it is a win in other +machines, this flag can be set in the ISA options. + +2022-07-18 Michael Meissner + +gcc/ + + * config/rs6000/rs6000.cc (rs6000_option_override_internal): + Remove code setting -mblock-ops-vector-pair by default on + power10. + +==================== work095, patch #2. + +Make BLOCK_OPTS options settable with ISA flags. + +In wanting to turn off block moves from generating load and store vector +pair operations on the power10, I noticed that the options for controlling +the code block moves generate (OPTION_MASK_BLOCK_OPS_UNALIGNED_VSX and +OPTION_MASK_BLOCK_OPS_VECTOR_PAIR) were not set in POWERPC_MASKS. It is +possible in future CPUs we might want to enable these options +automatically. This code moves these options to POWERPC_MASKS. + +2022-07-18 Michael Meissner + +gcc/ + + * config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Add + OPTION_MASK_BLOCK_OPS_VECTOR_PAIR and + OPTION_MASK_BLOCK_OPS_UNALIGNED_VSX. + +==================== work095, branch setup. + 2022-07-18 Michael Meissner Clone branch