[gcc(refs/users/meissner/heads/work095)] Revert patches.

[Michael Meissner <meissner@gcc.gnu.org>]

https://gcc.gnu.org/g:40c10c637bd1e57b2cb8b90dbecca586fbfa40f1

commit 40c10c637bd1e57b2cb8b90dbecca586fbfa40f1
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Jul 22 14:36:32 2022 -0400

    Revert patches.
    
    2022-07-19   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            Revert patches.
            * config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Add
            OPTION_MASK_BLOCK_OPS_VECTOR_PAIR.
            * config/rs6000/rs6000.opt (-mblock-ops-vector-pair): Add a
            comment.
    
    2022-07-21   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            Revert patches.
            * config/rs6000/rs6000.cc (rs6000_option_override_internal):
            Do not enable -mblock-ops-vector-pair by default on power10.

Diff:
---
 gcc/ChangeLog.meissner            | 170 ++++++++++++++++++++++++++++++++++++++
 gcc/config/rs6000/rs6000-cpus.def |   1 -
 gcc/config/rs6000/rs6000.cc       |  11 +++
 gcc/config/rs6000/rs6000.opt      |   2 -
 4 files changed, 181 insertions(+), 3 deletions(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index d36ddebdef0..61d24a87eae 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,173 @@
+==================== work095, patch #8.
+
+Support IEEE 128-bit overload test data built-in functions.
+
+This patch adds support for overloading the IEEE 128-bit test data and
+test data negate built-in functions bewteeen KFmode and TFmode arguments.
+
+2022-07-21   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/rs6000-builtins.def
+	(__builtin_vsx_scalar_test_data_class_qp_kf): Rename KFmode IEEE
+	128-bit test data built-in functions to have a KF suffix to allow
+	overloading.
+	(__builtin_vsx_scalar_test_neg_qp_kf): Likewise.
+	(__builtin_vsx_scalar_test_data_class_qp_tf): Add TFmode variants
+	for IEEE 128-bit insert and extract support.
+	(__builtin_vsx_scalar_test_neg_qp_tf): Likewise.
+	* config/rs6000/rs6000-overload.def
+	(__builtin_vec_scalar_test_data_class): Add TFmode overloads.
+	(__builtin_vec_scalar_test_neg): Likewise.
+	(__builtin_vec_scalar_test_neg_qp): Likewise.
+	(__builtin_vec_scalar_test_data_class_qp): Likewise.
+
+gcc/testsuite/
+
+	* gcc.target/powerpc/bfp/scalar-test-data-class-11.c:  Update the
+	expected error message.
+	* gcc.target/powerpc/bfp/scalar-test-neg-5.c: Likewise.
+
+==================== work095, patch #7.
+
+Support IEEE 128-bit overload extract and insert built-in functions.
+
+This patch adds support for overloading the IEEE 128-bit extract and
+insert built-in functions bewteeen KFmode and TFmode arguments.
+
+2022-07-21   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/rs6000-builtins.def
+	(__builtin_vsx_scalar_extract_expq_kf): Rename KFmode IEEE 128-bit
+	insert and extract built-in functions to have a KF suffix to allow
+	overloading.
+	(__builtin_vsx_scalar_extract_sigq_kf): Likewise.
+	(__builtin_vsx_scalar_insert_exp_qp_kf): Likewise.
+	(__builtin_vsx_scalar_extract_expq_tf): Add TFmode variants for
+	IEEE 128-bit insert and extract support.
+	(__builtin_vsx_scalar_extract_sigq_tf): Likewise.
+	(__builtin_vsx_scalar_insert_exp_qp_tf): Likewise.
+	* config/rs6000/rs6000-c.cc (altivec_resolve_overloaded_builtin):
+	Add support for having KFmode and TFmode variants of VSIEQPF.
+	* config/rs6000/rs6000-overload.def
+	(__builtin_vec_scalar_extract_exp): Add TFmode overloads.
+	(__builtin_vec_scalar_extract_sig): Likewise.
+	(__builtin_vec_scalar_insert_exp): Likewise.
+
+gcc/testsuite/
+
+	* gcc.target/powerpc/bfp/scalar-extract-exp-4.c:  Update the
+	expected error message.
+	* gcc.target/powerpc/bfp/scalar-extract-sig-4.c: Likewise.
+	* gcc.target/powerpc/bfp/scalar-insert-exp-10.c: Likewise.
+
+==================== work095, patch #6.
+
+Support IEEE 128-bit overload comparison built-in functions.
+
+This patch adds support for overloading the IEEE 128-bit comparison
+built-in functions bewteeen KFmode and TFmode arguments.
+
+2022-07-21   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/rs6000-builtins.def
+	(__builtin_vsx_scalar_cmp_exp_qp_eq_kf): Rename KFmode comparison
+	built-in functions to have a KF suffix to allow overloading.
+	(__builtin_vsx_scalar_cmp_exp_qp_gt_kf): Likewise.
+	(__builtin_vsx_scalar_cmp_exp_qp_lt_kf): Likewise.
+	(__builtin_vsx_scalar_cmp_exp_qp_unordered_kf): Likewise.
+	(__builtin_vsx_scalar_cmp_exp_qp_eq_tf): Add TFmode comparison
+	built-in functions.
+	(__builtin_vsx_scalar_cmp_exp_qp_gt_tf): Likewise.
+	(__builtin_vsx_scalar_cmp_exp_qp_lt_tf): Likewise.
+	(__builtin_vsx_scalar_cmp_exp_qp_unordered_tf): Likewise.
+	* config/rs6000/rs6000-overload.def
+	(__builtin_vec_scalar_cmp_exp_eq): Add TFmode overloaded
+	functions.
+	(__builtin_vec_scalar_cmp_exp_gt): Likewise.
+	(__builtin_vec_scalar_cmp_exp_lt): Likewise.
+	(__builtin_vec_scalar_cmp_exp_unordered): Likewise.
+
+==================== work095, patch #5.
+
+Support IEEE 128-bit overload round_to_odd built-in functions.
+
+This patch adds support for overloading the IEEE 128-bit round to odd
+built-in functions bewteeen KFmode and TFmode arguments.
+
+2022-07-21   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/rs6000-builtins.def
+	(__builtin_addf128_round_to_odd_kf): Rename KFmode round to odd
+	built-in functions with a KF suffix to allow overloading.
+	(__builtin_divf128_round_to_odd_kf): Likewise.
+	(__builtin_fmaf128_round_to_odd_kf): Likewise.
+	(__builtin_mulf128_round_to_odd_kf): Likewise.
+	(__builtin_sqrtf128_round_to_odd_kf): Likewise.
+	(__builtin_subf128_round_to_odd_kf): Likewise.
+	(__builtin_truncf128_round_to_odd_kf): Likewise.
+	(__builtin_addf128_round_to_odd_tf): Add TFmode round to odd
+	built-in functions.
+	(__builtin_fmaf128_round_to_odd_tf): Likewise.
+	(__builtin_mulf128_round_to_odd_tf): Likewise.
+	(__builtin_sqrtf128_round_to_odd_tf): Likewise.
+	(__builtin_subf128_round_to_odd_tf): Likewise.
+	(__builtin_truncf128_round_to_odd_tf): Likewise.
+	* config/rs6000/rs6000-overload.def
+	(__builtin_addf128_round_to_odd): Make IEEE 128-bit round to odd
+	built-in functions overloaded.
+	(__builtin_divf128_round_to_odd): Likewise.
+	(__builtin_fmaf128_round_to_odd): Likewise.
+	(__builtin_mulf128_round_to_odd): Likewise.
+	(__builtin_sqrtf128_round_to_odd): Likewise.
+	(__builtin_subf128_round_to_odd): Likewise.
+	(__builtin_truncf128_round_to_odd): Likewise.
+
+==================== work095, patch #4.
+
+IEEE 128-bit built-in support.
+
+This patch lays the ground work that future patches will use to add
+builtin support (both normal and overloaded) for the case where long
+double uses the IEEE 128-bit encoding.
+
+This adds a new stanza (ieee128-hw-ld) for when we have IEEE 128-bit
+hardware support and long double uses the IEEE 128-bit encoding.
+
+A new type attribute (ieeeld) is added for long double if long double uses
+the IEEE 128-bit encoding.
+
+2022-07-21   Michael Meissner  <meissner@linux.ibm.com>
+
+
+gcc/
+
+	* config/rs6000/rs6000-builtin.cc (rs6000_invalid_builtin): Add
+	support for ibm128-hw-ld stanza.
+	(rs6000_builtin_is_supported): Likewise.
+	(rs6000_init_builtins): Likewise.
+	(rs6000_expand_builtin): Add support for IEEE128_HW_LD.  Add
+	support for ieeeld.
+	* config/rs6000/rs6000-builtins.def (toplevel): Add comment about
+	the new ieeeld attribute.
+	* config/rs6000/rs6000-gen-builtins.cc (enum bif_stanza): Add
+	BSTZ_IEEE128_HW_LD.
+	(stanza_map): Likewise.
+	(enable_string): Likewise.
+	(attrinfo): Add isieeeld.
+	(parse_bif_attrs): Parse ieeeld.  Add printing ieeeld to the debug
+	print.
+	(write_decls): Add support for ibm128-hw-ld stanza and ieeeld
+	attribute.
+	(write_bif_static_init): Add support for ieeeld attribute.
+
 ==================== work095, patch #3.
 
 Make -mblock-ops-vector-pair option valid as an ISA option.
diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def
index 6ac6c526342..c3825bcccd8 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -122,7 +122,6 @@
 
 /* Mask of all options to set the default isa flags based on -mcpu=<xxx>.  */
 #define POWERPC_MASKS		(OPTION_MASK_ALTIVEC			\
-				 | OPTION_MASK_BLOCK_OPS_VECTOR_PAIR	\
 				 | OPTION_MASK_CMPB			\
 				 | OPTION_MASK_CRYPTO			\
 				 | OPTION_MASK_DFP			\
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 667f83b1dfd..3ff16b8ae04 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -4139,6 +4139,17 @@ rs6000_option_override_internal (bool global_init_p)
 	rs6000_isa_flags &= ~OPTION_MASK_BLOCK_OPS_UNALIGNED_VSX;
     }
 
+  if (!(rs6000_isa_flags_explicit & OPTION_MASK_BLOCK_OPS_VECTOR_PAIR))
+    {
+      /* Do not generate lxvp and stxvp on power10 since there are some
+	 performance issues.  */
+      if (TARGET_MMA && TARGET_EFFICIENT_UNALIGNED_VSX
+	  && rs6000_tune != PROCESSOR_POWER10)
+	rs6000_isa_flags |= OPTION_MASK_BLOCK_OPS_VECTOR_PAIR;
+      else
+	rs6000_isa_flags &= ~OPTION_MASK_BLOCK_OPS_VECTOR_PAIR;
+    }
+
   /* Use long double size to select the appropriate long double.  We use
      TYPE_PRECISION to differentiate the 3 different long double types.  We map
      128 into the precision used for TFmode.  */
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 39d6925b8f2..4931d781c4e 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -324,8 +324,6 @@ mblock-ops-unaligned-vsx
 Target Mask(BLOCK_OPS_UNALIGNED_VSX) Var(rs6000_isa_flags)
 Generate unaligned VSX load/store for inline expansion of memcpy/memmove.
 
-; Not set on power10 by default due to performance reasons, but it could be set
-; in future processors.
 mblock-ops-vector-pair
 Target Undocumented Mask(BLOCK_OPS_VECTOR_PAIR) Var(rs6000_isa_flags)
 Generate unaligned VSX vector pair load/store for inline expansion of memcpy/memmove.