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From: Michael Meissner <meissner@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work095)] Do not enable -mblock-ops-vector-pair. Date: Fri, 22 Jul 2022 18:43:58 +0000 (GMT) [thread overview] Message-ID: <20220722184358.BD2F43858405@sourceware.org> (raw) https://gcc.gnu.org/g:ee2f3cd73a71411b13e0f52acde94917e90718c5 commit ee2f3cd73a71411b13e0f52acde94917e90718c5 Author: Michael Meissner <meissner@linux.ibm.com> Date: Fri Jul 22 14:43:33 2022 -0400 Do not enable -mblock-ops-vector-pair. Testing has shown that using the load vector pair and store vector pair instructions for block moves has some performance issues on power10. A patch on June 11th modified the code so that GCC would not set -mblock-ops-vector-pair by default if we are tuning for power10, but it would set the option if we were tuning for a different machine and have load and store vector pair instructions enabled. This patch just eliminates the code setting -mblock-ops-vector-pair at all. 2022-07-22 Michael Meissner <meissner@linux.ibm.com> gcc/ * config/rs6000/rs6000.cc (rs6000_option_override_internal): Do not enable -mblock-ops-vector-pair by default on power10. Diff: --- gcc/config/rs6000/rs6000.cc | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 3ff16b8ae04..667f83b1dfd 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -4139,17 +4139,6 @@ rs6000_option_override_internal (bool global_init_p) rs6000_isa_flags &= ~OPTION_MASK_BLOCK_OPS_UNALIGNED_VSX; } - if (!(rs6000_isa_flags_explicit & OPTION_MASK_BLOCK_OPS_VECTOR_PAIR)) - { - /* Do not generate lxvp and stxvp on power10 since there are some - performance issues. */ - if (TARGET_MMA && TARGET_EFFICIENT_UNALIGNED_VSX - && rs6000_tune != PROCESSOR_POWER10) - rs6000_isa_flags |= OPTION_MASK_BLOCK_OPS_VECTOR_PAIR; - else - rs6000_isa_flags &= ~OPTION_MASK_BLOCK_OPS_VECTOR_PAIR; - } - /* Use long double size to select the appropriate long double. We use TYPE_PRECISION to differentiate the 3 different long double types. We map 128 into the precision used for TFmode. */
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