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From: Michael Meissner <meissner@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work095)] Allow IBM 128-bit to do offset addressing. Date: Sat, 23 Jul 2022 00:11:43 +0000 (GMT) [thread overview] Message-ID: <20220723001143.516403858405@sourceware.org> (raw) https://gcc.gnu.org/g:579acbc3080ad5d10cf8ff09f1b8cfb3aa4fe031 commit 579acbc3080ad5d10cf8ff09f1b8cfb3aa4fe031 Author: Michael Meissner <meissner@linux.ibm.com> Date: Fri Jul 22 20:10:13 2022 -0400 Allow IBM 128-bit to do offset addressing. I noticed that we didn't enable offset addressing for IBM 128-bit floating point. 2022-07-22 Michael Meissner <meissner@linux.ibm.com> gcc/ * config/rs6000/rs6000.cc (rs6000_setup_reg_addr_masks): Allow IFmode and possibly TFmode to use offset addressing. (reg_offset_addressing_ok_p): IBM 128-bit floating point modes can do offset addressing. Diff: --- gcc/config/rs6000/rs6000.cc | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 667f83b1dfd..ae61505123d 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -2697,6 +2697,11 @@ rs6000_setup_reg_addr_masks (void) || (rc == RELOAD_REG_VMX && TARGET_P9_VECTOR))))) addr_mask |= RELOAD_REG_OFFSET; + /* IBM 128-bit can do REG+OFFSET addressing. */ + else if ((addr_mask != 0) && !indexed_only_p + && FLOAT128_IBM_P (m)) + addr_mask |= RELOAD_REG_OFFSET; + /* VSX registers can do REG+OFFSET addresssing if ISA 3.0 instructions are enabled. The offset for 128-bit VSX registers is only 12-bits. While GPRs can handle the full offset range, VSX @@ -8511,6 +8516,16 @@ reg_offset_addressing_ok_p (machine_mode mode) { switch (mode) { + case E_IFmode: + return true; + + case E_TFmode: + if (FLOAT128_IBM_P (TFmode)) + return true; + + /* If TFmode is IEEE 128-bit, treat it like a vector. */ + /* fall through */ + case E_V16QImode: case E_V8HImode: case E_V4SFmode: @@ -8519,7 +8534,6 @@ reg_offset_addressing_ok_p (machine_mode mode) case E_V2DImode: case E_V1TImode: case E_TImode: - case E_TFmode: case E_KFmode: /* AltiVec/VSX vector modes. Only reg+reg addressing was valid until the ISA 3.0 vector d-form addressing mode was added. While TImode is not
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