From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1461) id 4E2C33857BAA; Fri, 29 Jul 2022 12:04:46 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 4E2C33857BAA MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Andrew Stubbs To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-1895] amdgcn: 64-bit vector shifts X-Act-Checkin: gcc X-Git-Author: Andrew Stubbs X-Git-Refname: refs/heads/master X-Git-Oldrev: 8f4d9c1dedac54942ad28cc1647d48959bec9e77 X-Git-Newrev: 6e0ca3fe88d8f98ba6b4009c9483e87afbcf4ee8 Message-Id: <20220729120446.4E2C33857BAA@sourceware.org> Date: Fri, 29 Jul 2022 12:04:46 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Jul 2022 12:04:46 -0000 https://gcc.gnu.org/g:6e0ca3fe88d8f98ba6b4009c9483e87afbcf4ee8 commit r13-1895-g6e0ca3fe88d8f98ba6b4009c9483e87afbcf4ee8 Author: Andrew Stubbs Date: Tue Jul 19 11:14:28 2022 +0100 amdgcn: 64-bit vector shifts Enable 64-bit vector-vector and vector-scalar shifts. gcc/ChangeLog: * config/gcn/gcn-valu.md (V_INT_noHI): New iterator. (3): Use V_INT_noHI. (v3): Likewise. Diff: --- gcc/config/gcn/gcn-valu.md | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md index abe46201344..8c33ae0c717 100644 --- a/gcc/config/gcn/gcn-valu.md +++ b/gcc/config/gcn/gcn-valu.md @@ -60,6 +60,8 @@ (define_mode_iterator V_INT_noQI [V64HI V64SI V64DI]) +(define_mode_iterator V_INT_noHI + [V64SI V64DI]) ; All of above (define_mode_iterator V_ALL @@ -2086,10 +2088,10 @@ }) (define_insn "3" - [(set (match_operand:V_SI 0 "register_operand" "= v") - (shiftop:V_SI - (match_operand:V_SI 1 "gcn_alu_operand" " v") - (vec_duplicate:V_SI + [(set (match_operand:V_INT_noHI 0 "register_operand" "= v") + (shiftop:V_INT_noHI + (match_operand:V_INT_noHI 1 "gcn_alu_operand" " v") + (vec_duplicate: (match_operand:SI 2 "gcn_alu_operand" "SvB"))))] "" "v_0\t%0, %2, %1" @@ -2117,10 +2119,10 @@ }) (define_insn "v3" - [(set (match_operand:V_SI 0 "register_operand" "=v") - (shiftop:V_SI - (match_operand:V_SI 1 "gcn_alu_operand" " v") - (match_operand:V_SI 2 "gcn_alu_operand" "vB")))] + [(set (match_operand:V_INT_noHI 0 "register_operand" "=v") + (shiftop:V_INT_noHI + (match_operand:V_INT_noHI 1 "gcn_alu_operand" " v") + (match_operand: 2 "gcn_alu_operand" "vB")))] "" "v_0\t%0, %2, %1" [(set_attr "type" "vop2")