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From: Andrew Stubbs <ams@gcc.gnu.org>
To: gcc-cvs@gcc.gnu.org
Subject: [gcc/devel/omp/gcc-12] amdgcn: 64-bit not
Date: Wed,  3 Aug 2022 09:30:10 +0000 (GMT)	[thread overview]
Message-ID: <20220803093010.51CD3385AC11@sourceware.org> (raw)

https://gcc.gnu.org/g:6b8d8ac8eabbb9959d888b88034fb68b8a54fda7

commit 6b8d8ac8eabbb9959d888b88034fb68b8a54fda7
Author: Andrew Stubbs <ams@codesourcery.com>
Date:   Fri Jul 15 15:28:44 2022 +0100

    amdgcn: 64-bit not
    
    This makes the auto-vectorizer happier when handling masks.
    
    gcc/ChangeLog:
    
            * config/gcn/gcn.md (one_cmpldi2): New.
    
    (cherry picked from commit 8f4d9c1dedac54942ad28cc1647d48959bec9e77)

Diff:
---
 gcc/ChangeLog.omp     |  5 +++++
 gcc/config/gcn/gcn.md | 20 ++++++++++++++++++++
 2 files changed, 25 insertions(+)

diff --git a/gcc/ChangeLog.omp b/gcc/ChangeLog.omp
index 7728dd9b2bf..c1de5d4f4ac 100644
--- a/gcc/ChangeLog.omp
+++ b/gcc/ChangeLog.omp
@@ -1,3 +1,8 @@
+2022-08-02  Andrew Stubbs  <ams@codesourcery.com>
+
+	Backport from mainline:
+	* config/gcn/gcn.md (one_cmpldi2): New.
+
 2022-08-01  Tobias Burnus  <tobias@codesourcery.com>
 
 	Backport from mainline:
diff --git a/gcc/config/gcn/gcn.md b/gcc/config/gcn/gcn.md
index 0f9381c9194..7197d2f5a2e 100644
--- a/gcc/config/gcn/gcn.md
+++ b/gcc/config/gcn/gcn.md
@@ -1709,6 +1709,26 @@
 ;; }}}
 ;; {{{ ALU: generic 64-bit
 
+(define_insn_and_split "one_cmpldi2"
+  [(set (match_operand:DI 0 "register_operand"        "=Sg,    v")
+	(not:DI (match_operand:DI 1 "gcn_alu_operand" "SgA,vSvDB")))
+   (clobber (match_scratch:BI 2			      "=cs,    X"))]
+  ""
+  "#"
+  "reload_completed"
+  [(parallel [(set (match_dup 3) (not:SI (match_dup 4)))
+	      (clobber (match_dup 2))])
+   (parallel [(set (match_dup 5) (not:SI (match_dup 6)))
+	      (clobber (match_dup 2))])]
+  {
+    operands[3] = gcn_operand_part (DImode, operands[0], 0);
+    operands[4] = gcn_operand_part (DImode, operands[1], 0);
+    operands[5] = gcn_operand_part (DImode, operands[0], 1);
+    operands[6] = gcn_operand_part (DImode, operands[1], 1);
+  }
+  [(set_attr "type" "mult")]
+)
+
 (define_code_iterator vec_and_scalar64_com [and ior xor])
 
 (define_insn_and_split "<expander>di3"


                 reply	other threads:[~2022-08-03  9:30 UTC|newest]

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