From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id E69253858430; Wed, 10 Aug 2022 18:45:09 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org E69253858430 Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work097)] Revert patch. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work097 X-Git-Oldrev: 410da5fc9813c0afa22996d9e4df299469aa5e55 X-Git-Newrev: bfe95056d95934d6e330ae9a75f2746082a6d72d Message-Id: <20220810184509.E69253858430@sourceware.org> Date: Wed, 10 Aug 2022 18:45:09 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 10 Aug 2022 18:45:10 -0000 https://gcc.gnu.org/g:bfe95056d95934d6e330ae9a75f2746082a6d72d commit bfe95056d95934d6e330ae9a75f2746082a6d72d Author: Michael Meissner Date: Wed Aug 10 14:44:34 2022 -0400 Revert patch. 2022-08-10 Michael Meissner gcc/ Revert patch. * config/rs6000/predicates.md (ieee128_operand): New predicate. (ibm128_operand): Likewise. * config/rs6000/rs6000.md (unpack): Use ibm128_operand instead of register_operand. (unpack_dm): Likewise. (unpack_nodm): Likewise. (pack_hard): Likewise. (unpack): Likewise. (truncsf2_hw): Use ieee128_operand instead of altivec_register_operand. (add3_odd): Likewise. (sub3_odd): Likewise. (mul3_odd): Likewise. (div3_odd): Likewise. (sqrt2_odd): Likewise. (fma4_odd): Likewise. (fms4_odd): Likewise. (nfma4_odd): Likewise. (nfms4_odd): Likewise. (truncdf2_odd): Likewise. * config/rs6000/vsx.md (xsxexpqp_): Use ieee128_operand instead of altivec_register_operand. (xsxsigqp_): Likewise. (xsiexpqpf_): Likewise. (xsiexpqp_): Likewise. (xscmpexpqp__): Likewise. (xscmpexpqp__): Likewise. (xststdcqp_): Likewise. (xststdcnegqp_): Likewise. (xststdcqp_" [(set (match_operand: 0 "nonimmediate_operand") (unspec: - [(match_operand:FMOVE128 1 "ibm128_operand") + [(match_operand:FMOVE128 1 "register_operand") (match_operand:QI 2 "const_0_to_1_operand")] UNSPEC_UNPACK_128BIT))] "FLOAT128_2REG_P (mode)" @@ -14623,7 +14623,7 @@ (define_insn_and_split "unpack_dm" [(set (match_operand: 0 "nonimmediate_operand" "=d,m,d,r,m") (unspec: - [(match_operand:FMOVE128 1 "ibm128_operand" "d,d,r,d,r") + [(match_operand:FMOVE128 1 "register_operand" "d,d,r,d,r") (match_operand:QI 2 "const_0_to_1_operand" "i,i,i,i,i")] UNSPEC_UNPACK_128BIT))] "TARGET_POWERPC64 && TARGET_DIRECT_MOVE && FLOAT128_2REG_P (mode)" @@ -14646,7 +14646,7 @@ (define_insn_and_split "unpack_nodm" [(set (match_operand: 0 "nonimmediate_operand" "=d,m,m") (unspec: - [(match_operand:FMOVE128 1 "ibm128_operand" "d,d,r") + [(match_operand:FMOVE128 1 "register_operand" "d,d,r") (match_operand:QI 2 "const_0_to_1_operand" "i,i,i")] UNSPEC_UNPACK_128BIT))] "(!TARGET_POWERPC64 || !TARGET_DIRECT_MOVE) && FLOAT128_2REG_P (mode)" @@ -14680,7 +14680,7 @@ }) (define_insn_and_split "pack_hard" - [(set (match_operand:FMOVE128 0 "ibm128_operand" "=&d") + [(set (match_operand:FMOVE128 0 "register_operand" "=&d") (unspec:FMOVE128 [(match_operand: 1 "register_operand" "d") (match_operand: 2 "register_operand" "d")] @@ -14733,7 +14733,7 @@ (define_insn "unpack" [(set (match_operand:DI 0 "register_operand" "=wa,wa") - (unspec:DI [(match_operand:FMOVE128_VSX 1 "ibm128_operand" "0,wa") + (unspec:DI [(match_operand:FMOVE128_VSX 1 "register_operand" "0,wa") (match_operand:QI 2 "const_0_to_1_operand" "O,i")] UNSPEC_UNPACK_128BIT))] "VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)" @@ -14747,7 +14747,7 @@ [(set_attr "type" "vecperm")]) (define_insn "pack" - [(set (match_operand:FMOVE128_VSX 0 "ibm128_operand" "=wa") + [(set (match_operand:FMOVE128_VSX 0 "register_operand" "=wa") (unspec:FMOVE128_VSX [(match_operand:DI 1 "register_operand" "wa") (match_operand:DI 2 "register_operand" "wa")] @@ -14984,7 +14984,7 @@ (define_insn_and_split "truncsf2_hw" [(set (match_operand:SF 0 "vsx_register_operand" "=wa") (float_truncate:SF - (match_operand:IEEE128 1 "ieee128_operand" "v"))) + (match_operand:IEEE128 1 "altivec_register_operand" "v"))) (clobber (match_scratch:DF 2 "=v"))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" "#" @@ -15213,10 +15213,10 @@ ;; IEEE 128-bit instructions with round to odd semantics (define_insn "add3_odd" - [(set (match_operand:IEEE128 0 "ieee128_operand" "=v") + [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") (unspec:IEEE128 - [(match_operand:IEEE128 1 "ieee128_operand" "v") - (match_operand:IEEE128 2 "ieee128_operand" "v")] + [(match_operand:IEEE128 1 "altivec_register_operand" "v") + (match_operand:IEEE128 2 "altivec_register_operand" "v")] UNSPEC_ADD_ROUND_TO_ODD))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" "xsaddqpo %0,%1,%2" @@ -15224,10 +15224,10 @@ (set_attr "size" "128")]) (define_insn "sub3_odd" - [(set (match_operand:IEEE128 0 "ieee128_operand" "=v") + [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") (unspec:IEEE128 - [(match_operand:IEEE128 1 "ieee128_operand" "v") - (match_operand:IEEE128 2 "ieee128_operand" "v")] + [(match_operand:IEEE128 1 "altivec_register_operand" "v") + (match_operand:IEEE128 2 "altivec_register_operand" "v")] UNSPEC_SUB_ROUND_TO_ODD))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" "xssubqpo %0,%1,%2" @@ -15235,10 +15235,10 @@ (set_attr "size" "128")]) (define_insn "mul3_odd" - [(set (match_operand:IEEE128 0 "ieee128_operand" "=v") + [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") (unspec:IEEE128 - [(match_operand:IEEE128 1 "ieee128_operand" "v") - (match_operand:IEEE128 2 "ieee128_operand" "v")] + [(match_operand:IEEE128 1 "altivec_register_operand" "v") + (match_operand:IEEE128 2 "altivec_register_operand" "v")] UNSPEC_MUL_ROUND_TO_ODD))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" "xsmulqpo %0,%1,%2" @@ -15246,10 +15246,10 @@ (set_attr "size" "128")]) (define_insn "div3_odd" - [(set (match_operand:IEEE128 0 "ieee128_operand" "=v") + [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") (unspec:IEEE128 - [(match_operand:IEEE128 1 "ieee128_operand" "v") - (match_operand:IEEE128 2 "ieee128_operand" "v")] + [(match_operand:IEEE128 1 "altivec_register_operand" "v") + (match_operand:IEEE128 2 "altivec_register_operand" "v")] UNSPEC_DIV_ROUND_TO_ODD))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" "xsdivqpo %0,%1,%2" @@ -15257,9 +15257,9 @@ (set_attr "size" "128")]) (define_insn "sqrt2_odd" - [(set (match_operand:IEEE128 0 "ieee128_operand" "=v") + [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") (unspec:IEEE128 - [(match_operand:IEEE128 1 "ieee128_operand" "v")] + [(match_operand:IEEE128 1 "altivec_register_operand" "v")] UNSPEC_SQRT_ROUND_TO_ODD))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" "xssqrtqpo %0,%1" @@ -15267,11 +15267,11 @@ (set_attr "size" "128")]) (define_insn "fma4_odd" - [(set (match_operand:IEEE128 0 "ieee128_operand" "=v") + [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") (unspec:IEEE128 - [(match_operand:IEEE128 1 "ieee128_operand" "v") - (match_operand:IEEE128 2 "ieee128_operand" "v") - (match_operand:IEEE128 3 "ieee128_operand" "0")] + [(match_operand:IEEE128 1 "altivec_register_operand" "v") + (match_operand:IEEE128 2 "altivec_register_operand" "v") + (match_operand:IEEE128 3 "altivec_register_operand" "0")] UNSPEC_FMA_ROUND_TO_ODD))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" "xsmaddqpo %0,%1,%2" @@ -15279,12 +15279,12 @@ (set_attr "size" "128")]) (define_insn "*fms4_odd" - [(set (match_operand:IEEE128 0 "ieee128_operand" "=v") + [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") (unspec:IEEE128 - [(match_operand:IEEE128 1 "ieee128_operand" "%v") - (match_operand:IEEE128 2 "ieee128_operand" "v") + [(match_operand:IEEE128 1 "altivec_register_operand" "%v") + (match_operand:IEEE128 2 "altivec_register_operand" "v") (neg:IEEE128 - (match_operand:IEEE128 3 "ieee128_operand" "0"))] + (match_operand:IEEE128 3 "altivec_register_operand" "0"))] UNSPEC_FMA_ROUND_TO_ODD))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" "xsmsubqpo %0,%1,%2" @@ -15292,12 +15292,12 @@ (set_attr "size" "128")]) (define_insn "*nfma4_odd" - [(set (match_operand:IEEE128 0 "ieee128_operand" "=v") + [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") (neg:IEEE128 (unspec:IEEE128 - [(match_operand:IEEE128 1 "ieee128_operand" "%v") - (match_operand:IEEE128 2 "ieee128_operand" "v") - (match_operand:IEEE128 3 "ieee128_operand" "0")] + [(match_operand:IEEE128 1 "altivec_register_operand" "%v") + (match_operand:IEEE128 2 "altivec_register_operand" "v") + (match_operand:IEEE128 3 "altivec_register_operand" "0")] UNSPEC_FMA_ROUND_TO_ODD)))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" "xsnmaddqpo %0,%1,%2" @@ -15305,13 +15305,13 @@ (set_attr "size" "128")]) (define_insn "*nfms4_odd" - [(set (match_operand:IEEE128 0 "ieee128_operand" "=v") + [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") (neg:IEEE128 (unspec:IEEE128 - [(match_operand:IEEE128 1 "ieee128_operand" "%v") - (match_operand:IEEE128 2 "ieee128_operand" "v") + [(match_operand:IEEE128 1 "altivec_register_operand" "%v") + (match_operand:IEEE128 2 "altivec_register_operand" "v") (neg:IEEE128 - (match_operand:IEEE128 3 "ieee128_operand" "0"))] + (match_operand:IEEE128 3 "altivec_register_operand" "0"))] UNSPEC_FMA_ROUND_TO_ODD)))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" "xsnmsubqpo %0,%1,%2" @@ -15320,7 +15320,7 @@ (define_insn "truncdf2_odd" [(set (match_operand:DF 0 "vsx_register_operand" "=v") - (unspec:DF [(match_operand:IEEE128 1 "ieee128_operand" "v")] + (unspec:DF [(match_operand:IEEE128 1 "altivec_register_operand" "v")] UNSPEC_TRUNC_ROUND_TO_ODD))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" "xscvqpdpo %0,%1" @@ -15330,8 +15330,8 @@ ;; IEEE 128-bit comparisons (define_insn "*cmp_hw" [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") - (compare:CCFP (match_operand:IEEE128 1 "ieee128_operand" "v") - (match_operand:IEEE128 2 "ieee128_operand" "v")))] + (compare:CCFP (match_operand:IEEE128 1 "altivec_register_operand" "v") + (match_operand:IEEE128 2 "altivec_register_operand" "v")))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" "xscmpuqp %0,%1,%2" [(set_attr "type" "veccmp") diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index c6b6b67d612..e226a93bbe5 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -5087,7 +5087,7 @@ ;; VSX Scalar Extract Exponent Quad-Precision (define_insn "xsxexpqp_" [(set (match_operand:DI 0 "altivec_register_operand" "=v") - (unspec:DI [(match_operand:IEEE128 1 "ieee128_operand" "v")] + (unspec:DI [(match_operand:IEEE128 1 "altivec_register_operand" "v")] UNSPEC_VSX_SXEXPDP))] "TARGET_P9_VECTOR" "xsxexpqp %0,%1" @@ -5105,7 +5105,7 @@ ;; VSX Scalar Extract Significand Quad-Precision (define_insn "xsxsigqp_" [(set (match_operand:TI 0 "altivec_register_operand" "=v") - (unspec:TI [(match_operand:IEEE128 1 "ieee128_operand" "v")] + (unspec:TI [(match_operand:IEEE128 1 "altivec_register_operand" "v")] UNSPEC_VSX_SXSIG))] "TARGET_P9_VECTOR" "xsxsigqp %0,%1" @@ -5122,9 +5122,9 @@ ;; VSX Scalar Insert Exponent Quad-Precision Floating Point Argument (define_insn "xsiexpqpf_" - [(set (match_operand:IEEE128 0 "ieee128_operand" "=v") + [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") (unspec:IEEE128 - [(match_operand:IEEE128 1 "ieee128_operand" "v") + [(match_operand:IEEE128 1 "altivec_register_operand" "v") (match_operand:DI 2 "altivec_register_operand" "v")] UNSPEC_VSX_SIEXPQP))] "TARGET_P9_VECTOR" @@ -5133,7 +5133,7 @@ ;; VSX Scalar Insert Exponent Quad-Precision (define_insn "xsiexpqp_" - [(set (match_operand:IEEE128 0 "ieee128_operand" "=v") + [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") (unspec:IEEE128 [(match_operand:TI 1 "altivec_register_operand" "v") (match_operand:DI 2 "altivec_register_operand" "v")] UNSPEC_VSX_SIEXPQP))] @@ -5200,8 +5200,8 @@ [(set (match_dup 3) (compare:CCFP (unspec:IEEE128 - [(match_operand:IEEE128 1 "ieee128_operand" "v") - (match_operand:IEEE128 2 "ieee128_operand" "v")] + [(match_operand:IEEE128 1 "vsx_register_operand" "v") + (match_operand:IEEE128 2 "vsx_register_operand" "v")] UNSPEC_VSX_SCMPEXPQP) (const_int 0))) (set (match_operand:SI 0 "register_operand" "=r") @@ -5221,8 +5221,8 @@ (define_insn "*xscmpexpqp" [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") (compare:CCFP - (unspec:IEEE128 [(match_operand:IEEE128 1 "ieee128_operand" "v") - (match_operand:IEEE128 2 "ieee128_operand" "v")] + (unspec:IEEE128 [(match_operand:IEEE128 1 "altivec_register_operand" "v") + (match_operand:IEEE128 2 "altivec_register_operand" "v")] UNSPEC_VSX_SCMPEXPQP) (match_operand:SI 3 "zero_constant" "j")))] "TARGET_P9_VECTOR" @@ -5238,7 +5238,7 @@ [(set (match_dup 3) (compare:CCFP (unspec:IEEE128 - [(match_operand:IEEE128 1 "ieee128_operand" "v") + [(match_operand:IEEE128 1 "altivec_register_operand" "v") (match_operand:SI 2 "u7bit_cint_operand" "n")] UNSPEC_VSX_STSTDC) (const_int 0))) @@ -5276,7 +5276,7 @@ [(set (match_dup 2) (compare:CCFP (unspec:IEEE128 - [(match_operand:IEEE128 1 "ieee128_operand" "v") + [(match_operand:IEEE128 1 "altivec_register_operand" "v") (const_int 0)] UNSPEC_VSX_STSTDC) (const_int 0))) @@ -5310,7 +5310,7 @@ [(set (match_operand:CCFP 0 "" "=y") (compare:CCFP (unspec:IEEE128 - [(match_operand:IEEE128 1 "ieee128_operand" "v") + [(match_operand:IEEE128 1 "altivec_register_operand" "v") (match_operand:SI 2 "u7bit_cint_operand" "n")] UNSPEC_VSX_STSTDC) (const_int 0)))]