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From: Michael Meissner <meissner@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work097)] Add predicates to inter-mix 128-bit floating point modes. Date: Thu, 11 Aug 2022 21:14:39 +0000 (GMT) [thread overview] Message-ID: <20220811211439.7B3FC3858C74@sourceware.org> (raw) https://gcc.gnu.org/g:c2cba75091610f7aa50f660f13eced005f78428b commit c2cba75091610f7aa50f660f13eced005f78428b Author: Michael Meissner <meissner@linux.ibm.com> Date: Thu Aug 11 17:14:20 2022 -0400 Add predicates to inter-mix 128-bit floating point modes. This patch adds two new predicates (ieee128_operand and ibm128_operand) that allow KFmode and TFmode to be used inter-changeably when long double is IEEE 128-bit, and IFmode and TFmode to be used inter-changeabily with long double is IBM 128-bit. The various built-in functions that use KFmode or IFmode have been modified to use these new predicates. The code in rs6000_expand_builtin that switched between the KFmode and TFmode built-in functions and the code that switched between the IFmode and TFmode built-in functions has been modified so it looks at the argument type. If a TFmode argument was passed, it will convert the built-in to from using KFmode or IFmode to one using TFmode. The nop conversion functions between IFmode and TFmode when long double uses IBM 128-bit have been extended so that they take GPR registers as well as FPR registers. This is to allow the test "pr105334.c" to pass. This test wants to use -msoft-float along with the __ibm128 pack/unpack functions. 2022-08-11 Michael Meissner <meissner@linux.ibm.com> gcc/ * config/rs6000/predicates.md (ieee128_operand): New predicate. (ibm128_operand): Likewise. * config/rs6000/rs6000-builtin.cc (rs6000_expand_builtin): Rework code that switches KFmode and IFmode built-in functions to TFmode to look at the argument's mode, and not just use the switch. * config/rs6000/rs6000.md (extendkftf2_internal): Add support for using GPR registers. (extendtfkf2_internal): Likewise. (extendiftf2_internal): Likewise. (extendtfif2_internal): Likewise. (unpack<mode>): Use ibm128_operand for TFmode/IFmode operands. (unpack<mode>_dm): Likewise. (unpack<mode>_nodm): Likewise. (pack<mode>_hard): Likewise. (unpack<mode>): Likewise. (pack<mode>): Likewise. (trunc<mode>sf2_hw): Use ieee128_operand for TFmode/KFmode operands. (add<mode>3_odd): Likewise. (sub<mode>3_odd): Likewise. (mul<mode>3_odd): Likewise. (div<mode>3_odd): Likewise. (sqrt<mode>2_odd): Likewise. (fma<mode>4_odd): Likewise. (fms<mode>4_odd): Likewise. (nfma<mode>4_odd): Likewise. (nfms<mode>4_odd): Likewise. (trunc<mode>df2_odd): Likewise. (cmp<mode>_hw): Likewise. * config/rs6000/vsx.md (xsxexpqp_<mode>): Likewise. (xsxsigqp_<mode>): Likewise. (xsiexpqpf_<mode): Likewise. (xsiexpqp_<mode>): Likewise. (xscmpexpqp_<code>_<mode>): Likewise. (xscmpexpqp_<code>_<mode>): Likewise. (xststdcqp_<mode>): Likewise. (xststdcnegqp_<mode): Likewise. (xststdcqp_<mode): Likewise. Diff: --- gcc/config/rs6000/predicates.md | 37 ++++++++ gcc/config/rs6000/rs6000-builtin.cc | 178 ++++++++++++++++++------------------ gcc/config/rs6000/rs6000.md | 102 +++++++++++---------- gcc/config/rs6000/vsx.md | 24 ++--- 4 files changed, 191 insertions(+), 150 deletions(-) diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index b1fcc69bb60..2839ca73d95 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -119,6 +119,43 @@ return VSX_REGNO_P (REGNO (op)); }) +;; Return 1 if op is an IEEE 128-bit floating point type that is in a +;; traditional Altivec register in order to do one of the IEEE 128-bit hardware +;; instructions. We allow the operand mode to be different from the mode in +;; the call to allow using either KFmode or TFmode, assuming the mode supports +;; IEEE 128-bits. This way combinations of long double and __float128 will +;; work when long double uses the IEEE 128-bit format without having to have +;; insns that recognize the pattern with convert insns used. +(define_predicate "ieee128_operand" + (match_code "reg,subreg") +{ + if (GET_MODE (op) != VOIDmode) + mode = GET_MODE (op); + + if (!FLOAT128_IEEE_P (mode)) + return 0; + + return altivec_register_operand (op, mode); +}) + +;; Return 1 if op is an IBM 128-bit floating point type. We allow the operand +;; mode to be different from the mode in the call to allow using either IFmode +;; or TFmode, assuming the mode supports IBM 128-bits. This way combinations +;; of long double and __ibm128 will work when long double uses the IBM 128-bit +;; format without having to have insns that recognize the pattern with convert +;; insns used. +(define_predicate "ibm128_operand" + (match_code "reg,subreg") +{ + if (GET_MODE (op) != VOIDmode) + mode = GET_MODE (op); + + if (!FLOAT128_IBM_P (mode)) + return 0; + + return register_operand (op, mode); +}) + ;; Return 1 if op is a vector register that operates on floating point vectors ;; (either altivec or VSX). (define_predicate "vfloat_operand" diff --git a/gcc/config/rs6000/rs6000-builtin.cc b/gcc/config/rs6000/rs6000-builtin.cc index 755a6b95db0..e34a8f0cebf 100644 --- a/gcc/config/rs6000/rs6000-builtin.cc +++ b/gcc/config/rs6000/rs6000-builtin.cc @@ -3293,78 +3293,96 @@ rs6000_expand_builtin (tree exp, rtx target, rtx /* subtarget */, size_t uns_fcode = (size_t)fcode; enum insn_code icode = rs6000_builtin_info[uns_fcode].icode; - /* TODO: The following commentary and code is inherited from the original - builtin processing code. The commentary is a bit confusing, with the - intent being that KFmode is always IEEE-128, IFmode is always IBM - double-double, and TFmode is the current long double. The code is - confusing in that it converts from KFmode to TFmode pattern names, - when the other direction is more intuitive. Try to address this. */ - - /* We have two different modes (KFmode, TFmode) that are the IEEE - 128-bit floating point type, depending on whether long double is the - IBM extended double (KFmode) or long double is IEEE 128-bit (TFmode). - It is simpler if we only define one variant of the built-in function, - and switch the code when defining it, rather than defining two built- - ins and using the overload table in rs6000-c.cc to switch between the - two. If we don't have the proper assembler, don't do this switch - because CODE_FOR_*kf* and CODE_FOR_*tf* will be CODE_FOR_nothing. */ - if (FLOAT128_IEEE_P (TFmode)) - switch (icode) - { - case CODE_FOR_sqrtkf2_odd: - icode = CODE_FOR_sqrttf2_odd; - break; - case CODE_FOR_trunckfdf2_odd: - icode = CODE_FOR_trunctfdf2_odd; - break; - case CODE_FOR_addkf3_odd: - icode = CODE_FOR_addtf3_odd; - break; - case CODE_FOR_subkf3_odd: - icode = CODE_FOR_subtf3_odd; - break; - case CODE_FOR_mulkf3_odd: - icode = CODE_FOR_multf3_odd; - break; - case CODE_FOR_divkf3_odd: - icode = CODE_FOR_divtf3_odd; - break; - case CODE_FOR_fmakf4_odd: - icode = CODE_FOR_fmatf4_odd; - break; - case CODE_FOR_xsxexpqp_kf: - icode = CODE_FOR_xsxexpqp_tf; - break; - case CODE_FOR_xsxsigqp_kf: - icode = CODE_FOR_xsxsigqp_tf; - break; - case CODE_FOR_xststdcnegqp_kf: - icode = CODE_FOR_xststdcnegqp_tf; - break; - case CODE_FOR_xsiexpqp_kf: - icode = CODE_FOR_xsiexpqp_tf; - break; - case CODE_FOR_xsiexpqpf_kf: - icode = CODE_FOR_xsiexpqpf_tf; - break; - case CODE_FOR_xststdcqp_kf: - icode = CODE_FOR_xststdcqp_tf; - break; - case CODE_FOR_xscmpexpqp_eq_kf: - icode = CODE_FOR_xscmpexpqp_eq_tf; - break; - case CODE_FOR_xscmpexpqp_lt_kf: - icode = CODE_FOR_xscmpexpqp_lt_tf; - break; - case CODE_FOR_xscmpexpqp_gt_kf: - icode = CODE_FOR_xscmpexpqp_gt_tf; - break; - case CODE_FOR_xscmpexpqp_unordered_kf: - icode = CODE_FOR_xscmpexpqp_unordered_tf; - break; - default: - break; - } + /* If we have a KFmode built-in function and long double uses the IEEE + 128-bit format, we have to convert the KFmode built-in to the similar + TFmode built-in. Similarly if we have a IFmode built-in function and long + double uses the IBM 128-bit format, we have to convert the IFmode built-in + to the similar TFmode built-in. */ + if (TARGET_FLOAT128_TYPE || TARGET_IBM128) + { + bifdata *bifaddr = &rs6000_builtin_info[uns_fcode]; + bool found_tf_mode = false; + int nargs = bifaddr->nargs; + for (int i = 0; i < nargs; i++) + { + tree arg = CALL_EXPR_ARG (exp, i); + if (arg != error_mark_node && TYPE_MODE (TREE_TYPE (arg)) == TFmode) + { + found_tf_mode = true; + break; + } + } + + /* Map all of the explicit KFmode functions to the TFmode alternate if + long double uses the IEEE 128-bit format. */ + if (found_tf_mode && FLOAT128_IEEE_P (TFmode)) + switch (icode) + { + case CODE_FOR_sqrtkf2_odd: + icode = CODE_FOR_sqrttf2_odd; + break; + case CODE_FOR_trunckfdf2_odd: + icode = CODE_FOR_trunctfdf2_odd; + break; + case CODE_FOR_addkf3_odd: + icode = CODE_FOR_addtf3_odd; + break; + case CODE_FOR_subkf3_odd: + icode = CODE_FOR_subtf3_odd; + break; + case CODE_FOR_mulkf3_odd: + icode = CODE_FOR_multf3_odd; + break; + case CODE_FOR_divkf3_odd: + icode = CODE_FOR_divtf3_odd; + break; + case CODE_FOR_fmakf4_odd: + icode = CODE_FOR_fmatf4_odd; + break; + case CODE_FOR_xsxexpqp_kf: + icode = CODE_FOR_xsxexpqp_tf; + break; + case CODE_FOR_xsxsigqp_kf: + icode = CODE_FOR_xsxsigqp_tf; + break; + case CODE_FOR_xststdcnegqp_kf: + icode = CODE_FOR_xststdcnegqp_tf; + break; + case CODE_FOR_xsiexpqp_kf: + icode = CODE_FOR_xsiexpqp_tf; + break; + case CODE_FOR_xsiexpqpf_kf: + icode = CODE_FOR_xsiexpqpf_tf; + break; + case CODE_FOR_xststdcqp_kf: + icode = CODE_FOR_xststdcqp_tf; + break; + case CODE_FOR_xscmpexpqp_eq_kf: + icode = CODE_FOR_xscmpexpqp_eq_tf; + break; + case CODE_FOR_xscmpexpqp_lt_kf: + icode = CODE_FOR_xscmpexpqp_lt_tf; + break; + case CODE_FOR_xscmpexpqp_gt_kf: + icode = CODE_FOR_xscmpexpqp_gt_tf; + break; + case CODE_FOR_xscmpexpqp_unordered_kf: + icode = CODE_FOR_xscmpexpqp_unordered_tf; + break; + default: + break; + } + + /* Map all of the explicit IFmode builtins to TFmode if long double uses + the IBM 128-bit format. */ + else if (found_tf_mode && FLOAT128_IBM_P (TFmode)) + { + if (icode == CODE_FOR_unpackif) + icode = CODE_FOR_unpacktf; + else if (icode == CODE_FOR_packif) + icode = CODE_FOR_packtf; + } + } /* In case of "#pragma target" changes, we initialize all builtins but check for actual availability now, during expand time. For @@ -3506,22 +3524,6 @@ rs6000_expand_builtin (tree exp, rtx target, rtx /* subtarget */, gcc_unreachable (); } - if (bif_is_ibm128 (*bifaddr) && TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD) - { - if (fcode == RS6000_BIF_PACK_IF) - { - icode = CODE_FOR_packtf; - fcode = RS6000_BIF_PACK_TF; - uns_fcode = (size_t) fcode; - } - else if (fcode == RS6000_BIF_UNPACK_IF) - { - icode = CODE_FOR_unpacktf; - fcode = RS6000_BIF_UNPACK_TF; - uns_fcode = (size_t) fcode; - } - } - /* TRUE iff the built-in function returns void. */ bool void_func = TREE_TYPE (TREE_TYPE (fndecl)) == void_type_node; /* Position of first argument (0 for void-returning functions, else 1). */ diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index e17252bb8de..10a610e9980 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -9143,9 +9143,9 @@ ;; Convert between KFmode and TFmode when -mabi=ieeelongdouble (define_insn_and_split "*extendkftf2_internal" - [(set (match_operand:TF 0 "gpc_reg_operand" "=wa,wa") + [(set (match_operand:TF 0 "gpc_reg_operand" "=wa,wa,r,r") (float_extend:TF - (match_operand:KF 1 "gpc_reg_operand" "0,wa")))] + (match_operand:KF 1 "gpc_reg_operand" "0,wa,0,r")))] "FLOAT128_IEEE_P (TFmode)" "#" "&& reload_completed" @@ -9153,12 +9153,13 @@ { operands[2] = gen_rtx_REG (TFmode, REGNO (operands[1])); } - [(set_attr "type" "vecsimple")]) + [(set_attr "type" "vecsimple,vecsimple,two,two") + (set_attr "num_insns" "*,*,2,2")]) (define_insn_and_split "*extendtfkf2_internal" - [(set (match_operand:KF 0 "gpc_reg_operand" "=wa,wa") + [(set (match_operand:KF 0 "gpc_reg_operand" "=wa,wa,r,r") (float_extend:KF - (match_operand:TF 1 "gpc_reg_operand" "0,wa")))] + (match_operand:TF 1 "gpc_reg_operand" "0,wa,0,r")))] "FLOAT128_IEEE_P (TFmode)" "#" "&& reload_completed" @@ -9166,13 +9167,14 @@ { operands[2] = gen_rtx_REG (KFmode, REGNO (operands[1])); } - [(set_attr "type" "vecsimple")]) + [(set_attr "type" "vecsimple,vecsimple,two,two") + (set_attr "num_insns" "*,*,2,2")]) ;; Convert between IFmode and TFmode when -mabi=ibmlongdouble (define_insn_and_split "*extendiftf2_internal" - [(set (match_operand:TF 0 "gpc_reg_operand" "=d,&d") + [(set (match_operand:TF 0 "gpc_reg_operand" "=d,&d,r,r") (float_extend:TF - (match_operand:IF 1 "input_operand" "0,d")))] + (match_operand:IF 1 "input_operand" "0,d,0,r")))] "FLOAT128_IBM_P (TFmode)" "#" "&& reload_completed" @@ -9190,9 +9192,9 @@ (set_attr "num_insns" "2")]) (define_insn_and_split "*extendtfif2_internal" - [(set (match_operand:IF 0 "gpc_reg_operand" "=d,&d") + [(set (match_operand:IF 0 "gpc_reg_operand" "=d,&d,r,&r") (float_extend:IF - (match_operand:TF 1 "input_operand" "0,d")))] + (match_operand:TF 1 "input_operand" "0,d,0,r")))] "FLOAT128_IBM_P (TFmode)" "#" "&& reload_completed" @@ -14614,7 +14616,7 @@ (define_expand "unpack<mode>" [(set (match_operand:<FP128_64> 0 "nonimmediate_operand") (unspec:<FP128_64> - [(match_operand:FMOVE128 1 "register_operand") + [(match_operand:FMOVE128 1 "ibm128_operand") (match_operand:QI 2 "const_0_to_1_operand")] UNSPEC_UNPACK_128BIT))] "FLOAT128_2REG_P (<MODE>mode)" @@ -14623,7 +14625,7 @@ (define_insn_and_split "unpack<mode>_dm" [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "=d,m,d,r,m") (unspec:<FP128_64> - [(match_operand:FMOVE128 1 "register_operand" "d,d,r,d,r") + [(match_operand:FMOVE128 1 "ibm128_operand" "d,d,r,d,r") (match_operand:QI 2 "const_0_to_1_operand" "i,i,i,i,i")] UNSPEC_UNPACK_128BIT))] "TARGET_POWERPC64 && TARGET_DIRECT_MOVE && FLOAT128_2REG_P (<MODE>mode)" @@ -14646,7 +14648,7 @@ (define_insn_and_split "unpack<mode>_nodm" [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "=d,m,m") (unspec:<FP128_64> - [(match_operand:FMOVE128 1 "register_operand" "d,d,r") + [(match_operand:FMOVE128 1 "ibm128_operand" "d,d,r") (match_operand:QI 2 "const_0_to_1_operand" "i,i,i")] UNSPEC_UNPACK_128BIT))] "(!TARGET_POWERPC64 || !TARGET_DIRECT_MOVE) && FLOAT128_2REG_P (<MODE>mode)" @@ -14680,7 +14682,7 @@ }) (define_insn_and_split "pack<mode>_hard" - [(set (match_operand:FMOVE128 0 "register_operand" "=&d") + [(set (match_operand:FMOVE128 0 "ibm128_operand" "=&d") (unspec:FMOVE128 [(match_operand:<FP128_64> 1 "register_operand" "d") (match_operand:<FP128_64> 2 "register_operand" "d")] @@ -14733,7 +14735,7 @@ (define_insn "unpack<mode>" [(set (match_operand:DI 0 "register_operand" "=wa,wa") - (unspec:DI [(match_operand:FMOVE128_VSX 1 "register_operand" "0,wa") + (unspec:DI [(match_operand:FMOVE128_VSX 1 "ibm128_operand" "0,wa") (match_operand:QI 2 "const_0_to_1_operand" "O,i")] UNSPEC_UNPACK_128BIT))] "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)" @@ -14747,7 +14749,7 @@ [(set_attr "type" "vecperm")]) (define_insn "pack<mode>" - [(set (match_operand:FMOVE128_VSX 0 "register_operand" "=wa") + [(set (match_operand:FMOVE128_VSX 0 "ibm128_operand" "=wa") (unspec:FMOVE128_VSX [(match_operand:DI 1 "register_operand" "wa") (match_operand:DI 2 "register_operand" "wa")] @@ -14984,7 +14986,7 @@ (define_insn_and_split "trunc<mode>sf2_hw" [(set (match_operand:SF 0 "vsx_register_operand" "=wa") (float_truncate:SF - (match_operand:IEEE128 1 "altivec_register_operand" "v"))) + (match_operand:IEEE128 1 "ieee128_operand" "v"))) (clobber (match_scratch:DF 2 "=v"))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" "#" @@ -15213,10 +15215,10 @@ ;; IEEE 128-bit instructions with round to odd semantics (define_insn "add<mode>3_odd" - [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") + [(set (match_operand:IEEE128 0 "ieee128_operand" "=v") (unspec:IEEE128 - [(match_operand:IEEE128 1 "altivec_register_operand" "v") - (match_operand:IEEE128 2 "altivec_register_operand" "v")] + [(match_operand:IEEE128 1 "ieee128_operand" "v") + (match_operand:IEEE128 2 "ieee128_operand" "v")] UNSPEC_ADD_ROUND_TO_ODD))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" "xsaddqpo %0,%1,%2" @@ -15224,10 +15226,10 @@ (set_attr "size" "128")]) (define_insn "sub<mode>3_odd" - [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") + [(set (match_operand:IEEE128 0 "ieee128_operand" "=v") (unspec:IEEE128 - [(match_operand:IEEE128 1 "altivec_register_operand" "v") - (match_operand:IEEE128 2 "altivec_register_operand" "v")] + [(match_operand:IEEE128 1 "ieee128_operand" "v") + (match_operand:IEEE128 2 "ieee128_operand" "v")] UNSPEC_SUB_ROUND_TO_ODD))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" "xssubqpo %0,%1,%2" @@ -15235,10 +15237,10 @@ (set_attr "size" "128")]) (define_insn "mul<mode>3_odd" - [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") + [(set (match_operand:IEEE128 0 "ieee128_operand" "=v") (unspec:IEEE128 - [(match_operand:IEEE128 1 "altivec_register_operand" "v") - (match_operand:IEEE128 2 "altivec_register_operand" "v")] + [(match_operand:IEEE128 1 "ieee128_operand" "v") + (match_operand:IEEE128 2 "ieee128_operand" "v")] UNSPEC_MUL_ROUND_TO_ODD))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" "xsmulqpo %0,%1,%2" @@ -15246,10 +15248,10 @@ (set_attr "size" "128")]) (define_insn "div<mode>3_odd" - [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") + [(set (match_operand:IEEE128 0 "ieee128_operand" "=v") (unspec:IEEE128 - [(match_operand:IEEE128 1 "altivec_register_operand" "v") - (match_operand:IEEE128 2 "altivec_register_operand" "v")] + [(match_operand:IEEE128 1 "ieee128_operand" "v") + (match_operand:IEEE128 2 "ieee128_operand" "v")] UNSPEC_DIV_ROUND_TO_ODD))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" "xsdivqpo %0,%1,%2" @@ -15257,9 +15259,9 @@ (set_attr "size" "128")]) (define_insn "sqrt<mode>2_odd" - [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") + [(set (match_operand:IEEE128 0 "ieee128_operand" "=v") (unspec:IEEE128 - [(match_operand:IEEE128 1 "altivec_register_operand" "v")] + [(match_operand:IEEE128 1 "ieee128_operand" "v")] UNSPEC_SQRT_ROUND_TO_ODD))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" "xssqrtqpo %0,%1" @@ -15267,11 +15269,11 @@ (set_attr "size" "128")]) (define_insn "fma<mode>4_odd" - [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") + [(set (match_operand:IEEE128 0 "ieee128_operand" "=v") (unspec:IEEE128 - [(match_operand:IEEE128 1 "altivec_register_operand" "v") - (match_operand:IEEE128 2 "altivec_register_operand" "v") - (match_operand:IEEE128 3 "altivec_register_operand" "0")] + [(match_operand:IEEE128 1 "ieee128_operand" "v") + (match_operand:IEEE128 2 "ieee128_operand" "v") + (match_operand:IEEE128 3 "ieee128_operand" "0")] UNSPEC_FMA_ROUND_TO_ODD))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" "xsmaddqpo %0,%1,%2" @@ -15279,12 +15281,12 @@ (set_attr "size" "128")]) (define_insn "*fms<mode>4_odd" - [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") + [(set (match_operand:IEEE128 0 "ieee128_operand" "=v") (unspec:IEEE128 - [(match_operand:IEEE128 1 "altivec_register_operand" "%v") - (match_operand:IEEE128 2 "altivec_register_operand" "v") + [(match_operand:IEEE128 1 "ieee128_operand" "%v") + (match_operand:IEEE128 2 "ieee128_operand" "v") (neg:IEEE128 - (match_operand:IEEE128 3 "altivec_register_operand" "0"))] + (match_operand:IEEE128 3 "ieee128_operand" "0"))] UNSPEC_FMA_ROUND_TO_ODD))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" "xsmsubqpo %0,%1,%2" @@ -15292,12 +15294,12 @@ (set_attr "size" "128")]) (define_insn "*nfma<mode>4_odd" - [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") + [(set (match_operand:IEEE128 0 "ieee128_operand" "=v") (neg:IEEE128 (unspec:IEEE128 - [(match_operand:IEEE128 1 "altivec_register_operand" "%v") - (match_operand:IEEE128 2 "altivec_register_operand" "v") - (match_operand:IEEE128 3 "altivec_register_operand" "0")] + [(match_operand:IEEE128 1 "ieee128_operand" "%v") + (match_operand:IEEE128 2 "ieee128_operand" "v") + (match_operand:IEEE128 3 "ieee128_operand" "0")] UNSPEC_FMA_ROUND_TO_ODD)))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" "xsnmaddqpo %0,%1,%2" @@ -15305,13 +15307,13 @@ (set_attr "size" "128")]) (define_insn "*nfms<mode>4_odd" - [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") + [(set (match_operand:IEEE128 0 "ieee128_operand" "=v") (neg:IEEE128 (unspec:IEEE128 - [(match_operand:IEEE128 1 "altivec_register_operand" "%v") - (match_operand:IEEE128 2 "altivec_register_operand" "v") + [(match_operand:IEEE128 1 "ieee128_operand" "%v") + (match_operand:IEEE128 2 "ieee128_operand" "v") (neg:IEEE128 - (match_operand:IEEE128 3 "altivec_register_operand" "0"))] + (match_operand:IEEE128 3 "ieee128_operand" "0"))] UNSPEC_FMA_ROUND_TO_ODD)))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" "xsnmsubqpo %0,%1,%2" @@ -15320,7 +15322,7 @@ (define_insn "trunc<mode>df2_odd" [(set (match_operand:DF 0 "vsx_register_operand" "=v") - (unspec:DF [(match_operand:IEEE128 1 "altivec_register_operand" "v")] + (unspec:DF [(match_operand:IEEE128 1 "ieee128_operand" "v")] UNSPEC_TRUNC_ROUND_TO_ODD))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" "xscvqpdpo %0,%1" @@ -15330,8 +15332,8 @@ ;; IEEE 128-bit comparisons (define_insn "*cmp<mode>_hw" [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") - (compare:CCFP (match_operand:IEEE128 1 "altivec_register_operand" "v") - (match_operand:IEEE128 2 "altivec_register_operand" "v")))] + (compare:CCFP (match_operand:IEEE128 1 "ieee128_operand" "v") + (match_operand:IEEE128 2 "ieee128_operand" "v")))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" "xscmpuqp %0,%1,%2" [(set_attr "type" "veccmp") diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index e226a93bbe5..c6b6b67d612 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -5087,7 +5087,7 @@ ;; VSX Scalar Extract Exponent Quad-Precision (define_insn "xsxexpqp_<mode>" [(set (match_operand:DI 0 "altivec_register_operand" "=v") - (unspec:DI [(match_operand:IEEE128 1 "altivec_register_operand" "v")] + (unspec:DI [(match_operand:IEEE128 1 "ieee128_operand" "v")] UNSPEC_VSX_SXEXPDP))] "TARGET_P9_VECTOR" "xsxexpqp %0,%1" @@ -5105,7 +5105,7 @@ ;; VSX Scalar Extract Significand Quad-Precision (define_insn "xsxsigqp_<mode>" [(set (match_operand:TI 0 "altivec_register_operand" "=v") - (unspec:TI [(match_operand:IEEE128 1 "altivec_register_operand" "v")] + (unspec:TI [(match_operand:IEEE128 1 "ieee128_operand" "v")] UNSPEC_VSX_SXSIG))] "TARGET_P9_VECTOR" "xsxsigqp %0,%1" @@ -5122,9 +5122,9 @@ ;; VSX Scalar Insert Exponent Quad-Precision Floating Point Argument (define_insn "xsiexpqpf_<mode>" - [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") + [(set (match_operand:IEEE128 0 "ieee128_operand" "=v") (unspec:IEEE128 - [(match_operand:IEEE128 1 "altivec_register_operand" "v") + [(match_operand:IEEE128 1 "ieee128_operand" "v") (match_operand:DI 2 "altivec_register_operand" "v")] UNSPEC_VSX_SIEXPQP))] "TARGET_P9_VECTOR" @@ -5133,7 +5133,7 @@ ;; VSX Scalar Insert Exponent Quad-Precision (define_insn "xsiexpqp_<mode>" - [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") + [(set (match_operand:IEEE128 0 "ieee128_operand" "=v") (unspec:IEEE128 [(match_operand:TI 1 "altivec_register_operand" "v") (match_operand:DI 2 "altivec_register_operand" "v")] UNSPEC_VSX_SIEXPQP))] @@ -5200,8 +5200,8 @@ [(set (match_dup 3) (compare:CCFP (unspec:IEEE128 - [(match_operand:IEEE128 1 "vsx_register_operand" "v") - (match_operand:IEEE128 2 "vsx_register_operand" "v")] + [(match_operand:IEEE128 1 "ieee128_operand" "v") + (match_operand:IEEE128 2 "ieee128_operand" "v")] UNSPEC_VSX_SCMPEXPQP) (const_int 0))) (set (match_operand:SI 0 "register_operand" "=r") @@ -5221,8 +5221,8 @@ (define_insn "*xscmpexpqp" [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") (compare:CCFP - (unspec:IEEE128 [(match_operand:IEEE128 1 "altivec_register_operand" "v") - (match_operand:IEEE128 2 "altivec_register_operand" "v")] + (unspec:IEEE128 [(match_operand:IEEE128 1 "ieee128_operand" "v") + (match_operand:IEEE128 2 "ieee128_operand" "v")] UNSPEC_VSX_SCMPEXPQP) (match_operand:SI 3 "zero_constant" "j")))] "TARGET_P9_VECTOR" @@ -5238,7 +5238,7 @@ [(set (match_dup 3) (compare:CCFP (unspec:IEEE128 - [(match_operand:IEEE128 1 "altivec_register_operand" "v") + [(match_operand:IEEE128 1 "ieee128_operand" "v") (match_operand:SI 2 "u7bit_cint_operand" "n")] UNSPEC_VSX_STSTDC) (const_int 0))) @@ -5276,7 +5276,7 @@ [(set (match_dup 2) (compare:CCFP (unspec:IEEE128 - [(match_operand:IEEE128 1 "altivec_register_operand" "v") + [(match_operand:IEEE128 1 "ieee128_operand" "v") (const_int 0)] UNSPEC_VSX_STSTDC) (const_int 0))) @@ -5310,7 +5310,7 @@ [(set (match_operand:CCFP 0 "" "=y") (compare:CCFP (unspec:IEEE128 - [(match_operand:IEEE128 1 "altivec_register_operand" "v") + [(match_operand:IEEE128 1 "ieee128_operand" "v") (match_operand:SI 2 "u7bit_cint_operand" "n")] UNSPEC_VSX_STSTDC) (const_int 0)))]
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