From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1984) id ED2E83858CDA; Fri, 12 Aug 2022 11:29:18 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org ED2E83858CDA MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Tamar Christina To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-2030] sve: Fix fcmuo combine patterns [PR106524] X-Act-Checkin: gcc X-Git-Author: Tamar Christina X-Git-Refname: refs/heads/master X-Git-Oldrev: 7e3b45befdbbf1a1f9ff728fa2bac31b4756907c X-Git-Newrev: f4ff20d464f90c85919ce2e7fa63e204dcda4e40 Message-Id: <20220812112918.ED2E83858CDA@sourceware.org> Date: Fri, 12 Aug 2022 11:29:18 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 12 Aug 2022 11:29:19 -0000 https://gcc.gnu.org/g:f4ff20d464f90c85919ce2e7fa63e204dcda4e40 commit r13-2030-gf4ff20d464f90c85919ce2e7fa63e204dcda4e40 Author: Tamar Christina Date: Fri Aug 12 12:28:41 2022 +0100 sve: Fix fcmuo combine patterns [PR106524] There's no encoding for fcmuo with zero. This restricts the combine patterns from accepting zero registers. gcc/ChangeLog: PR target/106524 * config/aarch64/aarch64-sve.md (*fcmuo_nor_combine, *fcmuo_bic_combine): Don't accept comparisons against zero. gcc/testsuite/ChangeLog: PR target/106524 * gcc.target/aarch64/sve/pr106524.c: New test. Diff: --- gcc/config/aarch64/aarch64-sve.md | 4 ++-- gcc/testsuite/gcc.target/aarch64/sve/pr106524.c | 11 +++++++++++ 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index bd60e65b0c3..e08bee197d8 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -8231,7 +8231,7 @@ [(match_operand: 1) (const_int SVE_KNOWN_PTRUE) (match_operand:SVE_FULL_F 2 "register_operand" "w") - (match_operand:SVE_FULL_F 3 "aarch64_simd_reg_or_zero" "wDz")] + (match_operand:SVE_FULL_F 3 "register_operand" "w")] UNSPEC_COND_FCMUO)) (match_operand: 4 "register_operand" "Upa")) (match_dup: 1))) @@ -8267,7 +8267,7 @@ [(match_operand: 1) (const_int SVE_KNOWN_PTRUE) (match_operand:SVE_FULL_F 2 "register_operand" "w") - (match_operand:SVE_FULL_F 3 "aarch64_simd_reg_or_zero" "wDz")] + (match_operand:SVE_FULL_F 3 "register_operand" "w")] UNSPEC_COND_FCMUO)) (not: (match_operand: 4 "register_operand" "Upa"))) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr106524.c b/gcc/testsuite/gcc.target/aarch64/sve/pr106524.c new file mode 100644 index 00000000000..a9f650f971a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/pr106524.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=armv8-a+sve -O2 -fno-move-loop-invariants" } */ + +void +test__zero (int *restrict dest, int *restrict src, float *a, int count) +{ + int i; + + for (i = 0; i < count; ++i) + dest[i] = !__builtin_isunordered (a[i], 0) ? src[i] : 0; +}