From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 598603858412; Fri, 12 Aug 2022 17:39:16 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 598603858412 Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work097)] Revert patches. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work097 X-Git-Oldrev: 7f9b5f23153244be5eec52bd466503e3fac8455b X-Git-Newrev: 1a4577b0e5da32f47ad718a2aa64afbc82714de4 Message-Id: <20220812173916.598603858412@sourceware.org> Date: Fri, 12 Aug 2022 17:39:16 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 12 Aug 2022 17:39:16 -0000 https://gcc.gnu.org/g:1a4577b0e5da32f47ad718a2aa64afbc82714de4 commit 1a4577b0e5da32f47ad718a2aa64afbc82714de4 Author: Michael Meissner Date: Fri Aug 12 13:37:12 2022 -0400 Revert patches. 2022-08-12 Michael Meissner gcc/ Revert patches * config/rs6000/rs6000-builtin.cc (rs6000_init_builtins): Always use the _Float128 type for __float128. Don't use the long double type. * config/rs6000/rs6000.cc (rs6000_libgcc_floating_mode_supported_p): Use KFmode for Float128 mode. (rs6000_floatn_mode): Likewise. (rs6000_c_mode_for_suffix): Likewise. 2022-08-11 Michael Meissner gcc/ Revert patches * config/rs6000/predicates.md (ieee128_operand): New predicate. (ibm128_operand): Likewise. * config/rs6000/rs6000-builtin.cc (rs6000_expand_builtin): Rework code that switches KFmode and IFmode built-in functions to TFmode to look at the argument's mode, and not just use the switch. * config/rs6000/rs6000.md (extendkftf2_internal): Add support for using GPR registers. (extendtfkf2_internal): Likewise. (extendiftf2_internal): Likewise. (extendtfif2_internal): Likewise. (unpack): Use ibm128_operand for TFmode/IFmode operands. (unpack_dm): Likewise. (unpack_nodm): Likewise. (pack_hard): Likewise. (unpack): Likewise. (pack): Likewise. (truncsf2_hw): Use ieee128_operand for TFmode/KFmode operands. (add3_odd): Likewise. (sub3_odd): Likewise. (mul3_odd): Likewise. (div3_odd): Likewise. (sqrt2_odd): Likewise. (fma4_odd): Likewise. (fms4_odd): Likewise. (nfma4_odd): Likewise. (nfms4_odd): Likewise. (truncdf2_odd): Likewise. (cmp_hw): Likewise. * config/rs6000/vsx.md (xsxexpqp_): Likewise. (xsxsigqp_): Likewise. (xsiexpqpf_): Likewise. (xscmpexpqp__): Likewise. (xscmpexpqp__): Likewise. (xststdcqp_): Likewise. (xststdcnegqp_ gcc/ Revert patches * config/rs6000/rs6000.md (IFKF): Delete. (IFKF_reg): Delete. (extendkfif2): New define_expand. (trunckfif2): New define_expand. (extendtf2_internal): Split into extendiftf2_internal and extendkftf2_internal. Update the insns to use the correct insn type and length attributes based on whether KFmode or IFmode is used. (extendiftf2_internal): Likewise. (extendkftf2_internal): Likewise. (extendtf2_internal): Split into extendtfif2_internal and extendtfkf2_internal. Update the insns to use the correct insn type and length attributes based on whether KFmode or IFmode is used. (extendtfif2_internal): Likewise. (extendtfkf2_internal): Likewise. 2022-08-12 Michael Meissner gcc/ Revert patches * ChangeLog.meissner: Update. Diff: --- gcc/ChangeLog.meissner | 109 +-------------------- gcc/config/rs6000/predicates.md | 37 ------- gcc/config/rs6000/rs6000-builtin.cc | 186 ++++++++++++++++++------------------ gcc/config/rs6000/rs6000.cc | 13 ++- gcc/config/rs6000/rs6000.md | 176 ++++++++++++---------------------- gcc/config/rs6000/vsx.md | 24 ++--- 6 files changed, 176 insertions(+), 369 deletions(-) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index a2ca1c84eb1..313e029b3fb 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -1,115 +1,12 @@ -==================== work097, patch009 - -Make __float128 use the _Float128 type. - -2022-08-12 Michael Meissner - -gcc/ - - * config/rs6000/rs6000-builtin.cc (rs6000_init_builtins): Always use the - _Float128 type for __float128. Don't use the long double type. - * config/rs6000/rs6000.cc (rs6000_libgcc_floating_mode_supported_p): - Use KFmode for Float128 mode. - (rs6000_floatn_mode): Likewise. - (rs6000_c_mode_for_suffix): Likewise. +==================== work097, patch009 was reverted ==================== work097, patch008 was reverted -==================== work097, patch007 - -Add predicates to inter-mix 128-bit floating point modes. - -This patch adds two new predicates (ieee128_operand and ibm128_operand) that -allow KFmode and TFmode to be used inter-changeably when long double is IEEE -128-bit, and IFmode and TFmode to be used inter-changeabily with long double is -IBM 128-bit. - -The various built-in functions that use KFmode or IFmode have been modified to -use these new predicates. - -The code in rs6000_expand_builtin that switched between the KFmode and TFmode -built-in functions and the code that switched between the IFmode and TFmode -built-in functions has been modified so it looks at the argument type. If a -TFmode argument was passed, it will convert the built-in to from using KFmode or -IFmode to one using TFmode. - -The nop conversion functions between IFmode and TFmode when long double uses IBM -128-bit have been extended so that they take GPR registers as well as FPR -registers. This is to allow the test "pr105334.c" to pass. This test wants to -use -msoft-float along with the __ibm128 pack/unpack functions. - -2022-08-11 Michael Meissner - -gcc/ - - * config/rs6000/predicates.md (ieee128_operand): New predicate. - (ibm128_operand): Likewise. - * config/rs6000/rs6000-builtin.cc (rs6000_expand_builtin): Rework code - that switches KFmode and IFmode built-in functions to TFmode to look at - the argument's mode, and not just use the switch. - * config/rs6000/rs6000.md (extendkftf2_internal): Add support for using - GPR registers. - (extendtfkf2_internal): Likewise. - (extendiftf2_internal): Likewise. - (extendtfif2_internal): Likewise. - (unpack): Use ibm128_operand for TFmode/IFmode operands. - (unpack_dm): Likewise. - (unpack_nodm): Likewise. - (pack_hard): Likewise. - (unpack): Likewise. - (pack): Likewise. - (truncsf2_hw): Use ieee128_operand for TFmode/KFmode operands. - (add3_odd): Likewise. - (sub3_odd): Likewise. - (mul3_odd): Likewise. - (div3_odd): Likewise. - (sqrt2_odd): Likewise. - (fma4_odd): Likewise. - (fms4_odd): Likewise. - (nfma4_odd): Likewise. - (nfms4_odd): Likewise. - (truncdf2_odd): Likewise. - (cmp_hw): Likewise. - * config/rs6000/vsx.md (xsxexpqp_): Likewise. - (xsxsigqp_): Likewise. - (xsiexpqpf_): Likewise. - (xscmpexpqp__): Likewise. - (xscmpexpqp__): Likewise. - (xststdcqp_): Likewise. - (xststdcnegqp_ - -gcc/ - - * config/rs6000/rs6000.md (IFKF): Delete. - (IFKF_reg): Delete. - (extendkfif2): New define_expand. - (trunckfif2): New define_expand. - (extendtf2_internal): Split into extendiftf2_internal and - extendkftf2_internal. Update the insns to use the correct insn type and - length attributes based on whether KFmode or IFmode is used. - (extendiftf2_internal): Likewise. - (extendkftf2_internal): Likewise. - (extendtf2_internal): Split into extendtfif2_internal and - extendtfkf2_internal. Update the insns to use the correct insn type and - length attributes based on whether KFmode or IFmode is used. - (extendtfif2_internal): Likewise. - (extendtfkf2_internal): Likewise. +==================== work097, patch005 was reverted ==================== work097, patch004 was reverted diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index 2839ca73d95..b1fcc69bb60 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -119,43 +119,6 @@ return VSX_REGNO_P (REGNO (op)); }) -;; Return 1 if op is an IEEE 128-bit floating point type that is in a -;; traditional Altivec register in order to do one of the IEEE 128-bit hardware -;; instructions. We allow the operand mode to be different from the mode in -;; the call to allow using either KFmode or TFmode, assuming the mode supports -;; IEEE 128-bits. This way combinations of long double and __float128 will -;; work when long double uses the IEEE 128-bit format without having to have -;; insns that recognize the pattern with convert insns used. -(define_predicate "ieee128_operand" - (match_code "reg,subreg") -{ - if (GET_MODE (op) != VOIDmode) - mode = GET_MODE (op); - - if (!FLOAT128_IEEE_P (mode)) - return 0; - - return altivec_register_operand (op, mode); -}) - -;; Return 1 if op is an IBM 128-bit floating point type. We allow the operand -;; mode to be different from the mode in the call to allow using either IFmode -;; or TFmode, assuming the mode supports IBM 128-bits. This way combinations -;; of long double and __ibm128 will work when long double uses the IBM 128-bit -;; format without having to have insns that recognize the pattern with convert -;; insns used. -(define_predicate "ibm128_operand" - (match_code "reg,subreg") -{ - if (GET_MODE (op) != VOIDmode) - mode = GET_MODE (op); - - if (!FLOAT128_IBM_P (mode)) - return 0; - - return register_operand (op, mode); -}) - ;; Return 1 if op is a vector register that operates on floating point vectors ;; (either altivec or VSX). (define_predicate "vfloat_operand" diff --git a/gcc/config/rs6000/rs6000-builtin.cc b/gcc/config/rs6000/rs6000-builtin.cc index 1cc97fa49b3..755a6b95db0 100644 --- a/gcc/config/rs6000/rs6000-builtin.cc +++ b/gcc/config/rs6000/rs6000-builtin.cc @@ -733,10 +733,10 @@ rs6000_init_builtins (void) if (TARGET_FLOAT128_TYPE) { - /* Always make the type used by __float128 to be the same as the - _Float128 type. The C23 standard will want long double to be a - different type than _Float128, so don't use the long double type. */ - ieee128_float_type_node = float128_type_node; + if (TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128) + ieee128_float_type_node = long_double_type_node; + else + ieee128_float_type_node = float128_type_node; t = build_qualified_type (ieee128_float_type_node, TYPE_QUAL_CONST); lang_hooks.types.register_builtin_type (ieee128_float_type_node, "__ieee128"); @@ -3293,96 +3293,78 @@ rs6000_expand_builtin (tree exp, rtx target, rtx /* subtarget */, size_t uns_fcode = (size_t)fcode; enum insn_code icode = rs6000_builtin_info[uns_fcode].icode; - /* If we have a KFmode built-in function and long double uses the IEEE - 128-bit format, we have to convert the KFmode built-in to the similar - TFmode built-in. Similarly if we have a IFmode built-in function and long - double uses the IBM 128-bit format, we have to convert the IFmode built-in - to the similar TFmode built-in. */ - if (TARGET_FLOAT128_TYPE || TARGET_IBM128) - { - bifdata *bifaddr = &rs6000_builtin_info[uns_fcode]; - bool found_tf_mode = false; - int nargs = bifaddr->nargs; - for (int i = 0; i < nargs; i++) - { - tree arg = CALL_EXPR_ARG (exp, i); - if (arg != error_mark_node && TYPE_MODE (TREE_TYPE (arg)) == TFmode) - { - found_tf_mode = true; - break; - } - } - - /* Map all of the explicit KFmode functions to the TFmode alternate if - long double uses the IEEE 128-bit format. */ - if (found_tf_mode && FLOAT128_IEEE_P (TFmode)) - switch (icode) - { - case CODE_FOR_sqrtkf2_odd: - icode = CODE_FOR_sqrttf2_odd; - break; - case CODE_FOR_trunckfdf2_odd: - icode = CODE_FOR_trunctfdf2_odd; - break; - case CODE_FOR_addkf3_odd: - icode = CODE_FOR_addtf3_odd; - break; - case CODE_FOR_subkf3_odd: - icode = CODE_FOR_subtf3_odd; - break; - case CODE_FOR_mulkf3_odd: - icode = CODE_FOR_multf3_odd; - break; - case CODE_FOR_divkf3_odd: - icode = CODE_FOR_divtf3_odd; - break; - case CODE_FOR_fmakf4_odd: - icode = CODE_FOR_fmatf4_odd; - break; - case CODE_FOR_xsxexpqp_kf: - icode = CODE_FOR_xsxexpqp_tf; - break; - case CODE_FOR_xsxsigqp_kf: - icode = CODE_FOR_xsxsigqp_tf; - break; - case CODE_FOR_xststdcnegqp_kf: - icode = CODE_FOR_xststdcnegqp_tf; - break; - case CODE_FOR_xsiexpqp_kf: - icode = CODE_FOR_xsiexpqp_tf; - break; - case CODE_FOR_xsiexpqpf_kf: - icode = CODE_FOR_xsiexpqpf_tf; - break; - case CODE_FOR_xststdcqp_kf: - icode = CODE_FOR_xststdcqp_tf; - break; - case CODE_FOR_xscmpexpqp_eq_kf: - icode = CODE_FOR_xscmpexpqp_eq_tf; - break; - case CODE_FOR_xscmpexpqp_lt_kf: - icode = CODE_FOR_xscmpexpqp_lt_tf; - break; - case CODE_FOR_xscmpexpqp_gt_kf: - icode = CODE_FOR_xscmpexpqp_gt_tf; - break; - case CODE_FOR_xscmpexpqp_unordered_kf: - icode = CODE_FOR_xscmpexpqp_unordered_tf; - break; - default: - break; - } - - /* Map all of the explicit IFmode builtins to TFmode if long double uses - the IBM 128-bit format. */ - else if (found_tf_mode && FLOAT128_IBM_P (TFmode)) - { - if (icode == CODE_FOR_unpackif) - icode = CODE_FOR_unpacktf; - else if (icode == CODE_FOR_packif) - icode = CODE_FOR_packtf; - } - } + /* TODO: The following commentary and code is inherited from the original + builtin processing code. The commentary is a bit confusing, with the + intent being that KFmode is always IEEE-128, IFmode is always IBM + double-double, and TFmode is the current long double. The code is + confusing in that it converts from KFmode to TFmode pattern names, + when the other direction is more intuitive. Try to address this. */ + + /* We have two different modes (KFmode, TFmode) that are the IEEE + 128-bit floating point type, depending on whether long double is the + IBM extended double (KFmode) or long double is IEEE 128-bit (TFmode). + It is simpler if we only define one variant of the built-in function, + and switch the code when defining it, rather than defining two built- + ins and using the overload table in rs6000-c.cc to switch between the + two. If we don't have the proper assembler, don't do this switch + because CODE_FOR_*kf* and CODE_FOR_*tf* will be CODE_FOR_nothing. */ + if (FLOAT128_IEEE_P (TFmode)) + switch (icode) + { + case CODE_FOR_sqrtkf2_odd: + icode = CODE_FOR_sqrttf2_odd; + break; + case CODE_FOR_trunckfdf2_odd: + icode = CODE_FOR_trunctfdf2_odd; + break; + case CODE_FOR_addkf3_odd: + icode = CODE_FOR_addtf3_odd; + break; + case CODE_FOR_subkf3_odd: + icode = CODE_FOR_subtf3_odd; + break; + case CODE_FOR_mulkf3_odd: + icode = CODE_FOR_multf3_odd; + break; + case CODE_FOR_divkf3_odd: + icode = CODE_FOR_divtf3_odd; + break; + case CODE_FOR_fmakf4_odd: + icode = CODE_FOR_fmatf4_odd; + break; + case CODE_FOR_xsxexpqp_kf: + icode = CODE_FOR_xsxexpqp_tf; + break; + case CODE_FOR_xsxsigqp_kf: + icode = CODE_FOR_xsxsigqp_tf; + break; + case CODE_FOR_xststdcnegqp_kf: + icode = CODE_FOR_xststdcnegqp_tf; + break; + case CODE_FOR_xsiexpqp_kf: + icode = CODE_FOR_xsiexpqp_tf; + break; + case CODE_FOR_xsiexpqpf_kf: + icode = CODE_FOR_xsiexpqpf_tf; + break; + case CODE_FOR_xststdcqp_kf: + icode = CODE_FOR_xststdcqp_tf; + break; + case CODE_FOR_xscmpexpqp_eq_kf: + icode = CODE_FOR_xscmpexpqp_eq_tf; + break; + case CODE_FOR_xscmpexpqp_lt_kf: + icode = CODE_FOR_xscmpexpqp_lt_tf; + break; + case CODE_FOR_xscmpexpqp_gt_kf: + icode = CODE_FOR_xscmpexpqp_gt_tf; + break; + case CODE_FOR_xscmpexpqp_unordered_kf: + icode = CODE_FOR_xscmpexpqp_unordered_tf; + break; + default: + break; + } /* In case of "#pragma target" changes, we initialize all builtins but check for actual availability now, during expand time. For @@ -3524,6 +3506,22 @@ rs6000_expand_builtin (tree exp, rtx target, rtx /* subtarget */, gcc_unreachable (); } + if (bif_is_ibm128 (*bifaddr) && TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD) + { + if (fcode == RS6000_BIF_PACK_IF) + { + icode = CODE_FOR_packtf; + fcode = RS6000_BIF_PACK_TF; + uns_fcode = (size_t) fcode; + } + else if (fcode == RS6000_BIF_UNPACK_IF) + { + icode = CODE_FOR_unpacktf; + fcode = RS6000_BIF_UNPACK_TF; + uns_fcode = (size_t) fcode; + } + } + /* TRUE iff the built-in function returns void. */ bool void_func = TREE_TYPE (TREE_TYPE (fndecl)) == void_type_node; /* Position of first argument (0 for void-returning functions, else 1). */ diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 88fc4f1fdc5..eddf8c8afe7 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -23724,8 +23724,13 @@ rs6000_libgcc_floating_mode_supported_p (scalar_float_mode mode) case E_TFmode: return true; + /* We only return true for KFmode if IEEE 128-bit types are supported, and + if long double does not use the IEEE 128-bit format. If long double + uses the IEEE 128-bit format, it will use TFmode and not KFmode. + Because the code will not use KFmode in that case, there will be aborts + because it can't find KFmode in the Floatn types. */ case E_KFmode: - return TARGET_FLOAT128_TYPE; + return TARGET_FLOAT128_TYPE && !TARGET_IEEEQUAD; default: return false; @@ -23759,7 +23764,7 @@ rs6000_floatn_mode (int n, bool extended) case 64: if (TARGET_FLOAT128_TYPE) - return KFmode; + return (FLOAT128_IEEE_P (TFmode)) ? TFmode : KFmode; else return opt_scalar_float_mode (); @@ -23783,7 +23788,7 @@ rs6000_floatn_mode (int n, bool extended) case 128: if (TARGET_FLOAT128_TYPE) - return KFmode; + return (FLOAT128_IEEE_P (TFmode)) ? TFmode : KFmode; else return opt_scalar_float_mode (); @@ -23801,7 +23806,7 @@ rs6000_c_mode_for_suffix (char suffix) if (TARGET_FLOAT128_TYPE) { if (suffix == 'q' || suffix == 'Q') - return KFmode; + return (FLOAT128_IEEE_P (TFmode)) ? TFmode : KFmode; /* At the moment, we are not defining a suffix for IBM extended double. If/when the default for -mabi=ieeelongdouble is changed, and we want diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 10a610e9980..f942597c3b4 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -543,6 +543,12 @@ ; Iterator for 128-bit VSX types for pack/unpack (define_mode_iterator FMOVE128_VSX [V1TI KF]) +; Iterators for converting to/from TFmode +(define_mode_iterator IFKF [IF KF]) + +; Constraints for moving IF/KFmode. +(define_mode_attr IFKF_reg [(IF "d") (KF "wa")]) + ; Whether a floating point move is ok, don't allow SD without hardware FP (define_mode_attr fmove_ok [(SF "") (DF "") @@ -9069,15 +9075,6 @@ DONE; }) -(define_expand "extendkfif2" - [(set (match_operand:IF 0 "gpc_reg_operand") - (float_extend:IF (match_operand:KF 1 "gpc_reg_operand")))] - "TARGET_FLOAT128_TYPE" -{ - rs6000_expand_float128_convert (operands[0], operands[1], false); - DONE; -}) - (define_expand "extendtfkf2" [(set (match_operand:KF 0 "gpc_reg_operand") (float_extend:KF (match_operand:TF 1 "gpc_reg_operand")))] @@ -9114,15 +9111,6 @@ DONE; }) -(define_expand "trunckfif2" - [(set (match_operand:IF 0 "gpc_reg_operand") - (float_truncate:IF (match_operand:KF 1 "gpc_reg_operand")))] - "TARGET_FLOAT128_TYPE" -{ - rs6000_expand_float128_convert (operands[0], operands[1], false); - DONE; -}) - (define_expand "trunckftf2" [(set (match_operand:TF 0 "gpc_reg_operand") (float_truncate:TF (match_operand:KF 1 "gpc_reg_operand")))] @@ -9141,75 +9129,31 @@ DONE; }) -;; Convert between KFmode and TFmode when -mabi=ieeelongdouble -(define_insn_and_split "*extendkftf2_internal" - [(set (match_operand:TF 0 "gpc_reg_operand" "=wa,wa,r,r") +(define_insn_and_split "*extendtf2_internal" + [(set (match_operand:TF 0 "gpc_reg_operand" "=") (float_extend:TF - (match_operand:KF 1 "gpc_reg_operand" "0,wa,0,r")))] - "FLOAT128_IEEE_P (TFmode)" + (match_operand:IFKF 1 "gpc_reg_operand" "")))] + "TARGET_FLOAT128_TYPE + && FLOAT128_IBM_P (TFmode) == FLOAT128_IBM_P (mode)" "#" "&& reload_completed" [(set (match_dup 0) (match_dup 2))] { operands[2] = gen_rtx_REG (TFmode, REGNO (operands[1])); -} - [(set_attr "type" "vecsimple,vecsimple,two,two") - (set_attr "num_insns" "*,*,2,2")]) +}) -(define_insn_and_split "*extendtfkf2_internal" - [(set (match_operand:KF 0 "gpc_reg_operand" "=wa,wa,r,r") - (float_extend:KF - (match_operand:TF 1 "gpc_reg_operand" "0,wa,0,r")))] - "FLOAT128_IEEE_P (TFmode)" +(define_insn_and_split "*extendtf2_internal" + [(set (match_operand:IFKF 0 "gpc_reg_operand" "=") + (float_extend:IFKF + (match_operand:TF 1 "gpc_reg_operand" "")))] + "TARGET_FLOAT128_TYPE + && FLOAT128_IBM_P (TFmode) == FLOAT128_IBM_P (mode)" "#" "&& reload_completed" [(set (match_dup 0) (match_dup 2))] { - operands[2] = gen_rtx_REG (KFmode, REGNO (operands[1])); -} - [(set_attr "type" "vecsimple,vecsimple,two,two") - (set_attr "num_insns" "*,*,2,2")]) - -;; Convert between IFmode and TFmode when -mabi=ibmlongdouble -(define_insn_and_split "*extendiftf2_internal" - [(set (match_operand:TF 0 "gpc_reg_operand" "=d,&d,r,r") - (float_extend:TF - (match_operand:IF 1 "input_operand" "0,d,0,r")))] - "FLOAT128_IBM_P (TFmode)" - "#" - "&& reload_completed" - [(set (match_dup 2) (match_dup 3)) - (set (match_dup 4) (match_dup 5))] -{ - unsigned int op0_regno = reg_or_subregno (operands[0]); - unsigned int op1_regno = reg_or_subregno (operands[1]); - operands[2] = gen_rtx_REG (DFmode, op0_regno); - operands[3] = gen_rtx_REG (DFmode, op1_regno); - operands[4] = gen_rtx_REG (DFmode, op0_regno + 1); - operands[5] = gen_rtx_REG (DFmode, op1_regno + 1); -} - [(set_attr "type" "two") - (set_attr "num_insns" "2")]) - -(define_insn_and_split "*extendtfif2_internal" - [(set (match_operand:IF 0 "gpc_reg_operand" "=d,&d,r,&r") - (float_extend:IF - (match_operand:TF 1 "input_operand" "0,d,0,r")))] - "FLOAT128_IBM_P (TFmode)" - "#" - "&& reload_completed" - [(set (match_dup 2) (match_dup 3)) - (set (match_dup 4) (match_dup 5))] -{ - unsigned int op0_regno = reg_or_subregno (operands[0]); - unsigned int op1_regno = reg_or_subregno (operands[1]); - operands[2] = gen_rtx_REG (DFmode, op0_regno); - operands[3] = gen_rtx_REG (DFmode, op1_regno); - operands[4] = gen_rtx_REG (DFmode, op0_regno + 1); - operands[5] = gen_rtx_REG (DFmode, op1_regno + 1); -} - [(set_attr "type" "two") - (set_attr "num_insns" "2")]) + operands[2] = gen_rtx_REG (mode, REGNO (operands[1])); +}) ;; Reload helper functions used by rs6000_secondary_reload. The patterns all @@ -14616,7 +14560,7 @@ (define_expand "unpack" [(set (match_operand: 0 "nonimmediate_operand") (unspec: - [(match_operand:FMOVE128 1 "ibm128_operand") + [(match_operand:FMOVE128 1 "register_operand") (match_operand:QI 2 "const_0_to_1_operand")] UNSPEC_UNPACK_128BIT))] "FLOAT128_2REG_P (mode)" @@ -14625,7 +14569,7 @@ (define_insn_and_split "unpack_dm" [(set (match_operand: 0 "nonimmediate_operand" "=d,m,d,r,m") (unspec: - [(match_operand:FMOVE128 1 "ibm128_operand" "d,d,r,d,r") + [(match_operand:FMOVE128 1 "register_operand" "d,d,r,d,r") (match_operand:QI 2 "const_0_to_1_operand" "i,i,i,i,i")] UNSPEC_UNPACK_128BIT))] "TARGET_POWERPC64 && TARGET_DIRECT_MOVE && FLOAT128_2REG_P (mode)" @@ -14648,7 +14592,7 @@ (define_insn_and_split "unpack_nodm" [(set (match_operand: 0 "nonimmediate_operand" "=d,m,m") (unspec: - [(match_operand:FMOVE128 1 "ibm128_operand" "d,d,r") + [(match_operand:FMOVE128 1 "register_operand" "d,d,r") (match_operand:QI 2 "const_0_to_1_operand" "i,i,i")] UNSPEC_UNPACK_128BIT))] "(!TARGET_POWERPC64 || !TARGET_DIRECT_MOVE) && FLOAT128_2REG_P (mode)" @@ -14682,7 +14626,7 @@ }) (define_insn_and_split "pack_hard" - [(set (match_operand:FMOVE128 0 "ibm128_operand" "=&d") + [(set (match_operand:FMOVE128 0 "register_operand" "=&d") (unspec:FMOVE128 [(match_operand: 1 "register_operand" "d") (match_operand: 2 "register_operand" "d")] @@ -14735,7 +14679,7 @@ (define_insn "unpack" [(set (match_operand:DI 0 "register_operand" "=wa,wa") - (unspec:DI [(match_operand:FMOVE128_VSX 1 "ibm128_operand" "0,wa") + (unspec:DI [(match_operand:FMOVE128_VSX 1 "register_operand" "0,wa") (match_operand:QI 2 "const_0_to_1_operand" "O,i")] UNSPEC_UNPACK_128BIT))] "VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)" @@ -14749,7 +14693,7 @@ [(set_attr "type" "vecperm")]) (define_insn "pack" - [(set (match_operand:FMOVE128_VSX 0 "ibm128_operand" "=wa") + [(set (match_operand:FMOVE128_VSX 0 "register_operand" "=wa") (unspec:FMOVE128_VSX [(match_operand:DI 1 "register_operand" "wa") (match_operand:DI 2 "register_operand" "wa")] @@ -14986,7 +14930,7 @@ (define_insn_and_split "truncsf2_hw" [(set (match_operand:SF 0 "vsx_register_operand" "=wa") (float_truncate:SF - (match_operand:IEEE128 1 "ieee128_operand" "v"))) + (match_operand:IEEE128 1 "altivec_register_operand" "v"))) (clobber (match_scratch:DF 2 "=v"))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" "#" @@ -15215,10 +15159,10 @@ ;; IEEE 128-bit instructions with round to odd semantics (define_insn "add3_odd" - [(set (match_operand:IEEE128 0 "ieee128_operand" "=v") + [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") (unspec:IEEE128 - [(match_operand:IEEE128 1 "ieee128_operand" "v") - (match_operand:IEEE128 2 "ieee128_operand" "v")] + [(match_operand:IEEE128 1 "altivec_register_operand" "v") + (match_operand:IEEE128 2 "altivec_register_operand" "v")] UNSPEC_ADD_ROUND_TO_ODD))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" "xsaddqpo %0,%1,%2" @@ -15226,10 +15170,10 @@ (set_attr "size" "128")]) (define_insn "sub3_odd" - [(set (match_operand:IEEE128 0 "ieee128_operand" "=v") + [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") (unspec:IEEE128 - [(match_operand:IEEE128 1 "ieee128_operand" "v") - (match_operand:IEEE128 2 "ieee128_operand" "v")] + [(match_operand:IEEE128 1 "altivec_register_operand" "v") + (match_operand:IEEE128 2 "altivec_register_operand" "v")] UNSPEC_SUB_ROUND_TO_ODD))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" "xssubqpo %0,%1,%2" @@ -15237,10 +15181,10 @@ (set_attr "size" "128")]) (define_insn "mul3_odd" - [(set (match_operand:IEEE128 0 "ieee128_operand" "=v") + [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") (unspec:IEEE128 - [(match_operand:IEEE128 1 "ieee128_operand" "v") - (match_operand:IEEE128 2 "ieee128_operand" "v")] + [(match_operand:IEEE128 1 "altivec_register_operand" "v") + (match_operand:IEEE128 2 "altivec_register_operand" "v")] UNSPEC_MUL_ROUND_TO_ODD))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" "xsmulqpo %0,%1,%2" @@ -15248,10 +15192,10 @@ (set_attr "size" "128")]) (define_insn "div3_odd" - [(set (match_operand:IEEE128 0 "ieee128_operand" "=v") + [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") (unspec:IEEE128 - [(match_operand:IEEE128 1 "ieee128_operand" "v") - (match_operand:IEEE128 2 "ieee128_operand" "v")] + [(match_operand:IEEE128 1 "altivec_register_operand" "v") + (match_operand:IEEE128 2 "altivec_register_operand" "v")] UNSPEC_DIV_ROUND_TO_ODD))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" "xsdivqpo %0,%1,%2" @@ -15259,9 +15203,9 @@ (set_attr "size" "128")]) (define_insn "sqrt2_odd" - [(set (match_operand:IEEE128 0 "ieee128_operand" "=v") + [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") (unspec:IEEE128 - [(match_operand:IEEE128 1 "ieee128_operand" "v")] + [(match_operand:IEEE128 1 "altivec_register_operand" "v")] UNSPEC_SQRT_ROUND_TO_ODD))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" "xssqrtqpo %0,%1" @@ -15269,11 +15213,11 @@ (set_attr "size" "128")]) (define_insn "fma4_odd" - [(set (match_operand:IEEE128 0 "ieee128_operand" "=v") + [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") (unspec:IEEE128 - [(match_operand:IEEE128 1 "ieee128_operand" "v") - (match_operand:IEEE128 2 "ieee128_operand" "v") - (match_operand:IEEE128 3 "ieee128_operand" "0")] + [(match_operand:IEEE128 1 "altivec_register_operand" "v") + (match_operand:IEEE128 2 "altivec_register_operand" "v") + (match_operand:IEEE128 3 "altivec_register_operand" "0")] UNSPEC_FMA_ROUND_TO_ODD))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" "xsmaddqpo %0,%1,%2" @@ -15281,12 +15225,12 @@ (set_attr "size" "128")]) (define_insn "*fms4_odd" - [(set (match_operand:IEEE128 0 "ieee128_operand" "=v") + [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") (unspec:IEEE128 - [(match_operand:IEEE128 1 "ieee128_operand" "%v") - (match_operand:IEEE128 2 "ieee128_operand" "v") + [(match_operand:IEEE128 1 "altivec_register_operand" "%v") + (match_operand:IEEE128 2 "altivec_register_operand" "v") (neg:IEEE128 - (match_operand:IEEE128 3 "ieee128_operand" "0"))] + (match_operand:IEEE128 3 "altivec_register_operand" "0"))] UNSPEC_FMA_ROUND_TO_ODD))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" "xsmsubqpo %0,%1,%2" @@ -15294,12 +15238,12 @@ (set_attr "size" "128")]) (define_insn "*nfma4_odd" - [(set (match_operand:IEEE128 0 "ieee128_operand" "=v") + [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") (neg:IEEE128 (unspec:IEEE128 - [(match_operand:IEEE128 1 "ieee128_operand" "%v") - (match_operand:IEEE128 2 "ieee128_operand" "v") - (match_operand:IEEE128 3 "ieee128_operand" "0")] + [(match_operand:IEEE128 1 "altivec_register_operand" "%v") + (match_operand:IEEE128 2 "altivec_register_operand" "v") + (match_operand:IEEE128 3 "altivec_register_operand" "0")] UNSPEC_FMA_ROUND_TO_ODD)))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" "xsnmaddqpo %0,%1,%2" @@ -15307,13 +15251,13 @@ (set_attr "size" "128")]) (define_insn "*nfms4_odd" - [(set (match_operand:IEEE128 0 "ieee128_operand" "=v") + [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") (neg:IEEE128 (unspec:IEEE128 - [(match_operand:IEEE128 1 "ieee128_operand" "%v") - (match_operand:IEEE128 2 "ieee128_operand" "v") + [(match_operand:IEEE128 1 "altivec_register_operand" "%v") + (match_operand:IEEE128 2 "altivec_register_operand" "v") (neg:IEEE128 - (match_operand:IEEE128 3 "ieee128_operand" "0"))] + (match_operand:IEEE128 3 "altivec_register_operand" "0"))] UNSPEC_FMA_ROUND_TO_ODD)))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" "xsnmsubqpo %0,%1,%2" @@ -15322,7 +15266,7 @@ (define_insn "truncdf2_odd" [(set (match_operand:DF 0 "vsx_register_operand" "=v") - (unspec:DF [(match_operand:IEEE128 1 "ieee128_operand" "v")] + (unspec:DF [(match_operand:IEEE128 1 "altivec_register_operand" "v")] UNSPEC_TRUNC_ROUND_TO_ODD))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" "xscvqpdpo %0,%1" @@ -15332,8 +15276,8 @@ ;; IEEE 128-bit comparisons (define_insn "*cmp_hw" [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") - (compare:CCFP (match_operand:IEEE128 1 "ieee128_operand" "v") - (match_operand:IEEE128 2 "ieee128_operand" "v")))] + (compare:CCFP (match_operand:IEEE128 1 "altivec_register_operand" "v") + (match_operand:IEEE128 2 "altivec_register_operand" "v")))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" "xscmpuqp %0,%1,%2" [(set_attr "type" "veccmp") diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index c6b6b67d612..e226a93bbe5 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -5087,7 +5087,7 @@ ;; VSX Scalar Extract Exponent Quad-Precision (define_insn "xsxexpqp_" [(set (match_operand:DI 0 "altivec_register_operand" "=v") - (unspec:DI [(match_operand:IEEE128 1 "ieee128_operand" "v")] + (unspec:DI [(match_operand:IEEE128 1 "altivec_register_operand" "v")] UNSPEC_VSX_SXEXPDP))] "TARGET_P9_VECTOR" "xsxexpqp %0,%1" @@ -5105,7 +5105,7 @@ ;; VSX Scalar Extract Significand Quad-Precision (define_insn "xsxsigqp_" [(set (match_operand:TI 0 "altivec_register_operand" "=v") - (unspec:TI [(match_operand:IEEE128 1 "ieee128_operand" "v")] + (unspec:TI [(match_operand:IEEE128 1 "altivec_register_operand" "v")] UNSPEC_VSX_SXSIG))] "TARGET_P9_VECTOR" "xsxsigqp %0,%1" @@ -5122,9 +5122,9 @@ ;; VSX Scalar Insert Exponent Quad-Precision Floating Point Argument (define_insn "xsiexpqpf_" - [(set (match_operand:IEEE128 0 "ieee128_operand" "=v") + [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") (unspec:IEEE128 - [(match_operand:IEEE128 1 "ieee128_operand" "v") + [(match_operand:IEEE128 1 "altivec_register_operand" "v") (match_operand:DI 2 "altivec_register_operand" "v")] UNSPEC_VSX_SIEXPQP))] "TARGET_P9_VECTOR" @@ -5133,7 +5133,7 @@ ;; VSX Scalar Insert Exponent Quad-Precision (define_insn "xsiexpqp_" - [(set (match_operand:IEEE128 0 "ieee128_operand" "=v") + [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") (unspec:IEEE128 [(match_operand:TI 1 "altivec_register_operand" "v") (match_operand:DI 2 "altivec_register_operand" "v")] UNSPEC_VSX_SIEXPQP))] @@ -5200,8 +5200,8 @@ [(set (match_dup 3) (compare:CCFP (unspec:IEEE128 - [(match_operand:IEEE128 1 "ieee128_operand" "v") - (match_operand:IEEE128 2 "ieee128_operand" "v")] + [(match_operand:IEEE128 1 "vsx_register_operand" "v") + (match_operand:IEEE128 2 "vsx_register_operand" "v")] UNSPEC_VSX_SCMPEXPQP) (const_int 0))) (set (match_operand:SI 0 "register_operand" "=r") @@ -5221,8 +5221,8 @@ (define_insn "*xscmpexpqp" [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") (compare:CCFP - (unspec:IEEE128 [(match_operand:IEEE128 1 "ieee128_operand" "v") - (match_operand:IEEE128 2 "ieee128_operand" "v")] + (unspec:IEEE128 [(match_operand:IEEE128 1 "altivec_register_operand" "v") + (match_operand:IEEE128 2 "altivec_register_operand" "v")] UNSPEC_VSX_SCMPEXPQP) (match_operand:SI 3 "zero_constant" "j")))] "TARGET_P9_VECTOR" @@ -5238,7 +5238,7 @@ [(set (match_dup 3) (compare:CCFP (unspec:IEEE128 - [(match_operand:IEEE128 1 "ieee128_operand" "v") + [(match_operand:IEEE128 1 "altivec_register_operand" "v") (match_operand:SI 2 "u7bit_cint_operand" "n")] UNSPEC_VSX_STSTDC) (const_int 0))) @@ -5276,7 +5276,7 @@ [(set (match_dup 2) (compare:CCFP (unspec:IEEE128 - [(match_operand:IEEE128 1 "ieee128_operand" "v") + [(match_operand:IEEE128 1 "altivec_register_operand" "v") (const_int 0)] UNSPEC_VSX_STSTDC) (const_int 0))) @@ -5310,7 +5310,7 @@ [(set (match_operand:CCFP 0 "" "=y") (compare:CCFP (unspec:IEEE128 - [(match_operand:IEEE128 1 "ieee128_operand" "v") + [(match_operand:IEEE128 1 "altivec_register_operand" "v") (match_operand:SI 2 "u7bit_cint_operand" "n")] UNSPEC_VSX_STSTDC) (const_int 0)))]