From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2098) id 2E16F385843D; Fri, 12 Aug 2022 18:59:55 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 2E16F385843D Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: SRINATH PARVATHANENI To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/vendors/ARM/heads/arm-12)] [Committed] arm: Document +no options for Cortex-M55 CPU. X-Act-Checkin: gcc X-Git-Author: Srinath Parvathaneni X-Git-Refname: refs/vendors/ARM/heads/arm-12 X-Git-Oldrev: 3df6552a395294b47db13dbe3ec9d9d429f92b6c X-Git-Newrev: 73b87442c19c1500b4f88ec60db712185149f5c5 Message-Id: <20220812185955.2E16F385843D@sourceware.org> Date: Fri, 12 Aug 2022 18:59:55 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 12 Aug 2022 18:59:55 -0000 https://gcc.gnu.org/g:73b87442c19c1500b4f88ec60db712185149f5c5 commit 73b87442c19c1500b4f88ec60db712185149f5c5 Author: Srinath Parvathaneni Date: Fri Aug 12 18:55:10 2022 +0100 [Committed] arm: Document +no options for Cortex-M55 CPU. Hi, This patch documents the following options for Arm Cortex-M55 CPU under -mcpu= list. +nomve.fp (disables MVE single precision floating point instructions) +nomve (disables MVE integer and single precision floating point instructions) +nodsp (disables dsp, MVE integer and single precision floating point instructions) +nofp (disables floating point instructions) Committed as obvious to master. Regards, Srinath. gcc/ChangeLog: 2022-08-12 Srinath Parvathaneni * doc/invoke.texi (Arm Options): Document -mcpu=cortex-m55 options. Diff: --- gcc/doc/invoke.texi | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index b6c7bcca58a..93ce6f89725 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -21151,14 +21151,25 @@ The following extension options are common to the listed CPUs: @table @samp @item +nodsp -Disable the DSP instructions on @samp{cortex-m33}, @samp{cortex-m35p}. +Disable the DSP instructions on @samp{cortex-m33}, @samp{cortex-m35p} +and @samp{cortex-m55}. Also disable the M-Profile Vector Extension (MVE) +integer and single precision floating-point instructions on @samp{cortex-m55}. + +@item +nomve +Disable the M-Profile Vector Extension (MVE) integer and single precision +floating-point instructions on @samp{cortex-m55}. + +@item +nomve.fp +Disable the M-Profile Vector Extension (MVE) single precision floating-point +instructions on @samp{cortex-m55}. @item +nofp Disables the floating-point instructions on @samp{arm9e}, @samp{arm946e-s}, @samp{arm966e-s}, @samp{arm968e-s}, @samp{arm10e}, @samp{arm1020e}, @samp{arm1022e}, @samp{arm926ej-s}, @samp{arm1026ej-s}, @samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-r8}, -@samp{cortex-m4}, @samp{cortex-m7}, @samp{cortex-m33} and @samp{cortex-m35p}. +@samp{cortex-m4}, @samp{cortex-m7}, @samp{cortex-m33}, @samp{cortex-m35p} +and @samp{cortex-m55}. Disables the floating-point and SIMD instructions on @samp{generic-armv7-a}, @samp{cortex-a5}, @samp{cortex-a7}, @samp{cortex-a8}, @samp{cortex-a9}, @samp{cortex-a12},