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From: Michael Meissner <meissner@gcc.gnu.org>
To: gcc-cvs@gcc.gnu.org
Subject: [gcc(refs/users/meissner/heads/work097)] Add ieee128_operand.
Date: Fri, 12 Aug 2022 19:28:30 +0000 (GMT) [thread overview]
Message-ID: <20220812192830.0329F3858D28@sourceware.org> (raw)
https://gcc.gnu.org/g:cf9a856f6754cab4b915b76aea03346e85c71326
commit cf9a856f6754cab4b915b76aea03346e85c71326
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Aug 12 15:28:13 2022 -0400
Add ieee128_operand.
Since we have 2 modes for IEEE 128-bit (KFmode and TFmode if long double is IEEE
128-bit), this patch provides a new predicate (ieee128_operand) that allows
combining a conversion from one mode to another.
For KFmode functions, we were are wanting a TFmode result (when long double uses
IEEE 128-bit), switch the built-in function to the same function using TFmode.
For IFmode functions, we were are wanting a TFmode result (when long double uses
IBM 128-bit), switch the built-in function to the same function using TFmode.
2022-08-12 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/predicates.md (ieee128_operand): New predicate.
* config/rs6000/rs6000.md (trunc<mode>sf2_hw): Use ieee128_operand.
(round<mode>2): Likewise.
(add<mode>3_odd): Likewise.
(sub<mode>3_odd): Likewise.
(mul<mode>3_odd): Likewise.
(div<mode>3_odd): Likewise.
(sqrt<mode>2_odd): Likewise.
(fma<mode>4_odd): Likewise.
(fms<mode>4_odd): Likewise.
(nfma<mode>4_odd): Likewise.
(nfms<mode>4_odd): Likewise.
(trunc<mode>df2_odd): Likewise.
* config/rs6000/vsx.md (xsxexpqp_<mode>): Likewise.
(xsxsigqp_<mode>): Likewise.
(xsiexpqpf_<mode>): Likewise.
(xscmpexpqp_<code>_<mode): Likewise.
(xscmpexpqp_<code>_<mode>): Likewise.
(xststdcqp_<mode>): Likewise.
(xststdcnegqp_<mode>): Likewise.
(xststdcqp_<mode>): Likewise.
Diff:
---
gcc/config/rs6000/predicates.md | 25 +++++++++++++++++++++
gcc/config/rs6000/rs6000.md | 50 ++++++++++++++++++++---------------------
gcc/config/rs6000/vsx.md | 20 ++++++++---------
3 files changed, 60 insertions(+), 35 deletions(-)
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index b1fcc69bb60..dfc6eb8aa83 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -119,6 +119,31 @@
return VSX_REGNO_P (REGNO (op));
})
+;; Return 1 if op is an IEEE 128-bit floating point type that is in a
+;; traditional Altivec register in order to do one of the IEEE 128-bit hardware
+;; instructions. We allow the operand to be converted from a mode that also
+;; supports IEEE 128-bit.
+(define_predicate "ieee128_operand"
+ (match_code "reg,subreg,float_extend,float_truncate")
+{
+ if (mode == VOIDmode)
+ mode = GET_MODE (op);
+
+ if (!FLOAT128_IEEE_P (mode))
+ return 0;
+
+ /* Allow conversions from another IEEE 128-bit mode. */
+ if (GET_CODE (op) == FLOAT_EXTEND || GET_CODE (op) == FLOAT_TRUNCATE)
+ {
+ op = XEXP (op, 0);
+ mode = GET_MODE (op);
+ if (!FLOAT128_IEEE_P (mode))
+ return 0;
+ }
+
+ return altivec_register_operand (op, mode);
+})
+
;; Return 1 if op is a vector register that operates on floating point vectors
;; (either altivec or VSX).
(define_predicate "vfloat_operand"
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index e17252bb8de..e0f6a3749a6 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -14984,7 +14984,7 @@
(define_insn_and_split "trunc<mode>sf2_hw"
[(set (match_operand:SF 0 "vsx_register_operand" "=wa")
(float_truncate:SF
- (match_operand:IEEE128 1 "altivec_register_operand" "v")))
+ (match_operand:IEEE128 1 "ieee128_operand" "v")))
(clobber (match_scratch:DF 2 "=v"))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"#"
@@ -15215,8 +15215,8 @@
(define_insn "add<mode>3_odd"
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(unspec:IEEE128
- [(match_operand:IEEE128 1 "altivec_register_operand" "v")
- (match_operand:IEEE128 2 "altivec_register_operand" "v")]
+ [(match_operand:IEEE128 1 "ieee128_operand" "v")
+ (match_operand:IEEE128 2 "ieee128_operand" "v")]
UNSPEC_ADD_ROUND_TO_ODD))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xsaddqpo %0,%1,%2"
@@ -15226,8 +15226,8 @@
(define_insn "sub<mode>3_odd"
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(unspec:IEEE128
- [(match_operand:IEEE128 1 "altivec_register_operand" "v")
- (match_operand:IEEE128 2 "altivec_register_operand" "v")]
+ [(match_operand:IEEE128 1 "ieee128_operand" "v")
+ (match_operand:IEEE128 2 "ieee128_operand" "v")]
UNSPEC_SUB_ROUND_TO_ODD))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xssubqpo %0,%1,%2"
@@ -15237,8 +15237,8 @@
(define_insn "mul<mode>3_odd"
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(unspec:IEEE128
- [(match_operand:IEEE128 1 "altivec_register_operand" "v")
- (match_operand:IEEE128 2 "altivec_register_operand" "v")]
+ [(match_operand:IEEE128 1 "ieee128_operand" "v")
+ (match_operand:IEEE128 2 "ieee128_operand" "v")]
UNSPEC_MUL_ROUND_TO_ODD))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xsmulqpo %0,%1,%2"
@@ -15248,8 +15248,8 @@
(define_insn "div<mode>3_odd"
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(unspec:IEEE128
- [(match_operand:IEEE128 1 "altivec_register_operand" "v")
- (match_operand:IEEE128 2 "altivec_register_operand" "v")]
+ [(match_operand:IEEE128 1 "ieee128_operand" "v")
+ (match_operand:IEEE128 2 "ieee128_operand" "v")]
UNSPEC_DIV_ROUND_TO_ODD))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xsdivqpo %0,%1,%2"
@@ -15259,7 +15259,7 @@
(define_insn "sqrt<mode>2_odd"
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(unspec:IEEE128
- [(match_operand:IEEE128 1 "altivec_register_operand" "v")]
+ [(match_operand:IEEE128 1 "ieee128_operand" "v")]
UNSPEC_SQRT_ROUND_TO_ODD))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xssqrtqpo %0,%1"
@@ -15269,9 +15269,9 @@
(define_insn "fma<mode>4_odd"
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(unspec:IEEE128
- [(match_operand:IEEE128 1 "altivec_register_operand" "v")
- (match_operand:IEEE128 2 "altivec_register_operand" "v")
- (match_operand:IEEE128 3 "altivec_register_operand" "0")]
+ [(match_operand:IEEE128 1 "ieee128_operand" "v")
+ (match_operand:IEEE128 2 "ieee128_operand" "v")
+ (match_operand:IEEE128 3 "ieee128_operand" "0")]
UNSPEC_FMA_ROUND_TO_ODD))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xsmaddqpo %0,%1,%2"
@@ -15281,10 +15281,10 @@
(define_insn "*fms<mode>4_odd"
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(unspec:IEEE128
- [(match_operand:IEEE128 1 "altivec_register_operand" "%v")
- (match_operand:IEEE128 2 "altivec_register_operand" "v")
+ [(match_operand:IEEE128 1 "ieee128_operand" "%v")
+ (match_operand:IEEE128 2 "ieee128_operand" "v")
(neg:IEEE128
- (match_operand:IEEE128 3 "altivec_register_operand" "0"))]
+ (match_operand:IEEE128 3 "ieee128_operand" "0"))]
UNSPEC_FMA_ROUND_TO_ODD))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xsmsubqpo %0,%1,%2"
@@ -15295,9 +15295,9 @@
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(neg:IEEE128
(unspec:IEEE128
- [(match_operand:IEEE128 1 "altivec_register_operand" "%v")
- (match_operand:IEEE128 2 "altivec_register_operand" "v")
- (match_operand:IEEE128 3 "altivec_register_operand" "0")]
+ [(match_operand:IEEE128 1 "ieee128_operand" "%v")
+ (match_operand:IEEE128 2 "ieee128_operand" "v")
+ (match_operand:IEEE128 3 "ieee128_operand" "0")]
UNSPEC_FMA_ROUND_TO_ODD)))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xsnmaddqpo %0,%1,%2"
@@ -15308,10 +15308,10 @@
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(neg:IEEE128
(unspec:IEEE128
- [(match_operand:IEEE128 1 "altivec_register_operand" "%v")
- (match_operand:IEEE128 2 "altivec_register_operand" "v")
+ [(match_operand:IEEE128 1 "ieee128_operand" "%v")
+ (match_operand:IEEE128 2 "ieee128_operand" "v")
(neg:IEEE128
- (match_operand:IEEE128 3 "altivec_register_operand" "0"))]
+ (match_operand:IEEE128 3 "ieee128_operand" "0"))]
UNSPEC_FMA_ROUND_TO_ODD)))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xsnmsubqpo %0,%1,%2"
@@ -15320,7 +15320,7 @@
(define_insn "trunc<mode>df2_odd"
[(set (match_operand:DF 0 "vsx_register_operand" "=v")
- (unspec:DF [(match_operand:IEEE128 1 "altivec_register_operand" "v")]
+ (unspec:DF [(match_operand:IEEE128 1 "ieee128_operand" "v")]
UNSPEC_TRUNC_ROUND_TO_ODD))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xscvqpdpo %0,%1"
@@ -15330,8 +15330,8 @@
;; IEEE 128-bit comparisons
(define_insn "*cmp<mode>_hw"
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
- (compare:CCFP (match_operand:IEEE128 1 "altivec_register_operand" "v")
- (match_operand:IEEE128 2 "altivec_register_operand" "v")))]
+ (compare:CCFP (match_operand:IEEE128 1 "ieee128_operand" "v")
+ (match_operand:IEEE128 2 "ieee128_operand" "v")))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xscmpuqp %0,%1,%2"
[(set_attr "type" "veccmp")
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index e226a93bbe5..03146223d1d 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -5087,7 +5087,7 @@
;; VSX Scalar Extract Exponent Quad-Precision
(define_insn "xsxexpqp_<mode>"
[(set (match_operand:DI 0 "altivec_register_operand" "=v")
- (unspec:DI [(match_operand:IEEE128 1 "altivec_register_operand" "v")]
+ (unspec:DI [(match_operand:IEEE128 1 "ieee128_operand" "v")]
UNSPEC_VSX_SXEXPDP))]
"TARGET_P9_VECTOR"
"xsxexpqp %0,%1"
@@ -5105,7 +5105,7 @@
;; VSX Scalar Extract Significand Quad-Precision
(define_insn "xsxsigqp_<mode>"
[(set (match_operand:TI 0 "altivec_register_operand" "=v")
- (unspec:TI [(match_operand:IEEE128 1 "altivec_register_operand" "v")]
+ (unspec:TI [(match_operand:IEEE128 1 "ieee128_operand" "v")]
UNSPEC_VSX_SXSIG))]
"TARGET_P9_VECTOR"
"xsxsigqp %0,%1"
@@ -5124,7 +5124,7 @@
(define_insn "xsiexpqpf_<mode>"
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(unspec:IEEE128
- [(match_operand:IEEE128 1 "altivec_register_operand" "v")
+ [(match_operand:IEEE128 1 "ieee128_operand" "v")
(match_operand:DI 2 "altivec_register_operand" "v")]
UNSPEC_VSX_SIEXPQP))]
"TARGET_P9_VECTOR"
@@ -5200,8 +5200,8 @@
[(set (match_dup 3)
(compare:CCFP
(unspec:IEEE128
- [(match_operand:IEEE128 1 "vsx_register_operand" "v")
- (match_operand:IEEE128 2 "vsx_register_operand" "v")]
+ [(match_operand:IEEE128 1 "ieee128_operand" "v")
+ (match_operand:IEEE128 2 "ieee128_operand" "v")]
UNSPEC_VSX_SCMPEXPQP)
(const_int 0)))
(set (match_operand:SI 0 "register_operand" "=r")
@@ -5221,8 +5221,8 @@
(define_insn "*xscmpexpqp"
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
(compare:CCFP
- (unspec:IEEE128 [(match_operand:IEEE128 1 "altivec_register_operand" "v")
- (match_operand:IEEE128 2 "altivec_register_operand" "v")]
+ (unspec:IEEE128 [(match_operand:IEEE128 1 "ieee128_operand" "v")
+ (match_operand:IEEE128 2 "ieee128_operand" "v")]
UNSPEC_VSX_SCMPEXPQP)
(match_operand:SI 3 "zero_constant" "j")))]
"TARGET_P9_VECTOR"
@@ -5238,7 +5238,7 @@
[(set (match_dup 3)
(compare:CCFP
(unspec:IEEE128
- [(match_operand:IEEE128 1 "altivec_register_operand" "v")
+ [(match_operand:IEEE128 1 "ieee128_operand" "v")
(match_operand:SI 2 "u7bit_cint_operand" "n")]
UNSPEC_VSX_STSTDC)
(const_int 0)))
@@ -5276,7 +5276,7 @@
[(set (match_dup 2)
(compare:CCFP
(unspec:IEEE128
- [(match_operand:IEEE128 1 "altivec_register_operand" "v")
+ [(match_operand:IEEE128 1 "ieee128_operand" "v")
(const_int 0)]
UNSPEC_VSX_STSTDC)
(const_int 0)))
@@ -5310,7 +5310,7 @@
[(set (match_operand:CCFP 0 "" "=y")
(compare:CCFP
(unspec:IEEE128
- [(match_operand:IEEE128 1 "altivec_register_operand" "v")
+ [(match_operand:IEEE128 1 "ieee128_operand" "v")
(match_operand:SI 2 "u7bit_cint_operand" "n")]
UNSPEC_VSX_STSTDC)
(const_int 0)))]
reply other threads:[~2022-08-12 19:28 UTC|newest]
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