From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 9E0873858C2F; Fri, 12 Aug 2022 19:50:30 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 9E0873858C2F Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work097)] Add ibm128_operand. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work097 X-Git-Oldrev: cf9a856f6754cab4b915b76aea03346e85c71326 X-Git-Newrev: 2a5743f93d34412aaac3ce380da4a9ae96de7329 Message-Id: <20220812195030.9E0873858C2F@sourceware.org> Date: Fri, 12 Aug 2022 19:50:30 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 12 Aug 2022 19:50:30 -0000 https://gcc.gnu.org/g:2a5743f93d34412aaac3ce380da4a9ae96de7329 commit 2a5743f93d34412aaac3ce380da4a9ae96de7329 Author: Michael Meissner Date: Fri Aug 12 15:50:11 2022 -0400 Add ibm128_operand. Since we have 2 modes for IBM 128-bit (IFmode and TFmode if long double is IBM 128-bit), this patch provides a new predicate (ibm128_operand) that allows combining a conversion from one mode to another. 2022-08-12 Michael Meissner gcc/ * config/rs6000/predicates.md (ibm128_operand): New predicate. * config/rs6000/rs6000.md (extendiftf2_internal): Add GPR registers in case -msoft-float is used. (extendtfif2_internal): Likewise. (unpack): Use ibm128_operand. (unpack_dm): Likewise. (unpack_nodm): Likewise. Diff: --- gcc/config/rs6000/predicates.md | 23 +++++++++++++++++++++++ gcc/config/rs6000/rs6000.md | 15 +++++++-------- 2 files changed, 30 insertions(+), 8 deletions(-) diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index dfc6eb8aa83..5bbb5c30bbb 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -144,6 +144,29 @@ return altivec_register_operand (op, mode); }) +;; Return 1 if op is an IBM 128-bit floating point type. We allow the operand +;; to be converted from a mode that also supports IBM 128-bit. +(define_predicate "ibm128_operand" + (match_code "reg,subreg,float_extend,float_truncate") +{ + if (mode == VOIDmode) + mode = GET_MODE (op); + + if (!FLOAT128_IBM_P (mode)) + return 0; + + /* Allow conversions from another IBM 128-bit mode. */ + if (GET_CODE (op) == FLOAT_EXTEND || GET_CODE (op) == FLOAT_TRUNCATE) + { + op = XEXP (op, 0); + mode = GET_MODE (op); + if (!FLOAT128_IBM_P (mode)) + return 0; + } + + return register_operand (op, mode); +}) + ;; Return 1 if op is a vector register that operates on floating point vectors ;; (either altivec or VSX). (define_predicate "vfloat_operand" diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index e0f6a3749a6..1905e4cc6c6 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -9170,9 +9170,9 @@ ;; Convert between IFmode and TFmode when -mabi=ibmlongdouble (define_insn_and_split "*extendiftf2_internal" - [(set (match_operand:TF 0 "gpc_reg_operand" "=d,&d") + [(set (match_operand:TF 0 "gpc_reg_operand" "=d,&d,r,r") (float_extend:TF - (match_operand:IF 1 "input_operand" "0,d")))] + (match_operand:IF 1 "input_operand" "0,d,0,r")))] "FLOAT128_IBM_P (TFmode)" "#" "&& reload_completed" @@ -9190,9 +9190,9 @@ (set_attr "num_insns" "2")]) (define_insn_and_split "*extendtfif2_internal" - [(set (match_operand:IF 0 "gpc_reg_operand" "=d,&d") + [(set (match_operand:IF 0 "gpc_reg_operand" "=d,&d,r,&r") (float_extend:IF - (match_operand:TF 1 "input_operand" "0,d")))] + (match_operand:TF 1 "input_operand" "0,d,0,r")))] "FLOAT128_IBM_P (TFmode)" "#" "&& reload_completed" @@ -14614,7 +14614,7 @@ (define_expand "unpack" [(set (match_operand: 0 "nonimmediate_operand") (unspec: - [(match_operand:FMOVE128 1 "register_operand") + [(match_operand:FMOVE128 1 "ibm128_operand") (match_operand:QI 2 "const_0_to_1_operand")] UNSPEC_UNPACK_128BIT))] "FLOAT128_2REG_P (mode)" @@ -14623,7 +14623,7 @@ (define_insn_and_split "unpack_dm" [(set (match_operand: 0 "nonimmediate_operand" "=d,m,d,r,m") (unspec: - [(match_operand:FMOVE128 1 "register_operand" "d,d,r,d,r") + [(match_operand:FMOVE128 1 "ibm128_operand" "d,d,r,d,r") (match_operand:QI 2 "const_0_to_1_operand" "i,i,i,i,i")] UNSPEC_UNPACK_128BIT))] "TARGET_POWERPC64 && TARGET_DIRECT_MOVE && FLOAT128_2REG_P (mode)" @@ -14646,7 +14646,7 @@ (define_insn_and_split "unpack_nodm" [(set (match_operand: 0 "nonimmediate_operand" "=d,m,m") (unspec: - [(match_operand:FMOVE128 1 "register_operand" "d,d,r") + [(match_operand:FMOVE128 1 "ibm128_operand" "d,d,r") (match_operand:QI 2 "const_0_to_1_operand" "i,i,i")] UNSPEC_UNPACK_128BIT))] "(!TARGET_POWERPC64 || !TARGET_DIRECT_MOVE) && FLOAT128_2REG_P (mode)" @@ -14756,7 +14756,6 @@ "xxpermdi %x0,%x1,%x2,0" [(set_attr "type" "vecperm")]) - ;; ISA 2.08 IEEE 128-bit floating point support.