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From: Andrew Pinski <pinskia@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/pinskia/heads/riscvbit)] [RISCV] have b ISA extension enable zba, zbb, zbc and zbs ISA extensions Date: Mon, 15 Aug 2022 23:13:39 +0000 (GMT) [thread overview] Message-ID: <20220815231339.242F93858422@sourceware.org> (raw) https://gcc.gnu.org/g:e2688326256ca637c183c55f3f9d73024dc071ff commit e2688326256ca637c183c55f3f9d73024dc071ff Author: Andrew Pinski <apinski@marvell.com> Date: Thu Aug 4 16:40:15 2022 -0700 [RISCV] have b ISA extension enable zba, zbb, zbc and zbs ISA extensions This patch allows the b ISA extension to be supply and will enable all 4 of the sections of the ISA extensions. OK? Built and tested on riscv32-elf with --with-arch==rv32iabmc . Signed-off-by: Andrew Pinski <apinski@marvell.com> gcc/ChangeLog: PR target/106531 * common/config/riscv/riscv-common.cc: Change-Id: Ic7e06760f4f6f6f4627185c67ced397c094023fd Diff: --- gcc/common/config/riscv/riscv-common.cc | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 0e5be2ce105..ac257daecfa 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -65,6 +65,11 @@ static const riscv_implied_info_t riscv_implied_info[] = {"zks", "zksed"}, {"zks", "zksh"}, + {"b", "zba"}, + {"b", "zbb"}, + {"b", "zbc"}, + {"b", "zbs"}, + {"v", "zvl128b"}, {"v", "zve64d"}, @@ -149,6 +154,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0}, {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0}, + {"b", ISA_SPEC_CLASS_NONE, 1, 0}, {"zba", ISA_SPEC_CLASS_NONE, 1, 0}, {"zbb", ISA_SPEC_CLASS_NONE, 1, 0}, {"zbc", ISA_SPEC_CLASS_NONE, 1, 0},
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