From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1314) id 7E5923858281; Mon, 15 Aug 2022 23:14:04 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 7E5923858281 Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Andrew Pinski To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/pinskia/heads/riscvbit)] Add the list of operand modifiers to riscv.md too X-Act-Checkin: gcc X-Git-Author: Andrew Pinski X-Git-Refname: refs/users/pinskia/heads/riscvbit X-Git-Oldrev: ad17c841878a4acece8c81a400070754332fe369 X-Git-Newrev: 28994ef3339e1fb45b64c9614320088e99f7695f Message-Id: <20220815231404.7E5923858281@sourceware.org> Date: Mon, 15 Aug 2022 23:14:04 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 15 Aug 2022 23:14:04 -0000 https://gcc.gnu.org/g:28994ef3339e1fb45b64c9614320088e99f7695f commit 28994ef3339e1fb45b64c9614320088e99f7695f Author: Andrew Pinski Date: Fri Aug 12 17:19:36 2022 +0000 Add the list of operand modifiers to riscv.md too gcc/ChangeLog: * config/riscv/riscv.cc (riscv_memmodel_needs_release_fence): * config/riscv/riscv.md: Change-Id: I544fcee1780ff45ae89afff3edf755390eb67673 Diff: --- gcc/config/riscv/riscv.cc | 4 +++- gcc/config/riscv/riscv.md | 14 ++++++++++++++ 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 5a0adffb5ce..38854b42309 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -3673,7 +3673,9 @@ riscv_memmodel_needs_release_fence (enum memmodel model) 'z' Print x0 if OP is zero, otherwise print OP normally. 'i' Print i if the operand is not a register. 'S' Print shift-index of single-bit mask OP. - 'T' Print shift-index of inverted single-bit mask OP. */ + 'T' Print shift-index of inverted single-bit mask OP. + + Note please keep this list and the list in riscv.md in sync. */ static void riscv_print_operand (FILE *file, rtx op, int letter) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index a76b12cff81..5c775040ac3 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -19,6 +19,20 @@ ;; along with GCC; see the file COPYING3. If not see ;; . + +;; Keep this list and the one above riscv_print_operand in sync. +;; The special asm out single letter directives following a '%' are: +;; h -- Print the high-part relocation associated with OP, after stripping +;; any outermost HIGH. +;; R -- Print the low-part relocation associated with OP. +;; C -- Print the integer branch condition for comparison OP. +;; A -- Print the atomic operation suffix for memory model OP. +;; F -- Print a FENCE if the memory model requires a release. +;; z -- Print x0 if OP is zero, otherwise print OP normally. +;; i -- Print i if the operand is not a register. +;; S -- Print shift-index of single-bit mask OP. +;; T -- Print shift-index of inverted single-bit mask OP. + (define_c_enum "unspec" [ ;; Override return address for exception handling. UNSPEC_EH_RETURN