From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1314) id 8F799385828F; Mon, 15 Aug 2022 23:14:09 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 8F799385828F Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Andrew Pinski To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/pinskia/heads/riscvbit)] [RISCV] Add %~ to print w if TARGET_64BIT and use it X-Act-Checkin: gcc X-Git-Author: Andrew Pinski X-Git-Refname: refs/users/pinskia/heads/riscvbit X-Git-Oldrev: 28994ef3339e1fb45b64c9614320088e99f7695f X-Git-Newrev: 8e4eee491862ce843af945d590063832ee2f2906 Message-Id: <20220815231409.8F799385828F@sourceware.org> Date: Mon, 15 Aug 2022 23:14:09 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 15 Aug 2022 23:14:09 -0000 https://gcc.gnu.org/g:8e4eee491862ce843af945d590063832ee2f2906 commit 8e4eee491862ce843af945d590063832ee2f2906 Author: Andrew Pinski Date: Fri Aug 12 17:46:16 2022 +0000 [RISCV] Add %~ to print w if TARGET_64BIT and use it To make things easier and more maintainable, we need to add support printing out w if TARGET_64BIT so this patch adds %~ to do that, simiilar how the x86 backend uses %~ to print out i/f for TARGET_AVX2. OK? Build and tested for riscv64-linux-gnu with no regressions. gcc/ChangeLog: * config/riscv/bitmanip.md: * config/riscv/riscv.cc (riscv_print_operand): (riscv_print_operand_punct_valid_p): (TARGET_PRINT_OPERAND_PUNCT_VALID_P): * config/riscv/riscv.md: Change-Id: I83ae3c7398735fa85f27c6cec211ff8160aa3c80 Diff: --- gcc/config/riscv/bitmanip.md | 6 +++--- gcc/config/riscv/riscv.cc | 19 +++++++++++++++++++ gcc/config/riscv/riscv.md | 15 ++++++++------- 3 files changed, 30 insertions(+), 10 deletions(-) diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index 3329dd54eb6..ebd6eee1a22 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -143,7 +143,7 @@ [(set (match_operand:SI 0 "register_operand" "=r") (clz_ctz_pcnt:SI (match_operand:SI 1 "register_operand" "r")))] "TARGET_ZBB" - { return TARGET_64BIT ? "w\t%0,%1" : "\t%0,%1"; } + "%~\t%0,%1" [(set_attr "type" "bitmanip") (set_attr "mode" "SI")]) @@ -201,7 +201,7 @@ (rotatert:SI (match_operand:SI 1 "register_operand" "r") (match_operand:QI 2 "arith_operand" "rI")))] "TARGET_ZBB" - { return TARGET_64BIT ? "ror%i2w\t%0,%1,%2" : "ror%i2\t%0,%1,%2"; } + "ror%i2%~\t%0,%1,%2" [(set_attr "type" "bitmanip")]) (define_insn "rotrdi3" @@ -225,7 +225,7 @@ (rotate:SI (match_operand:SI 1 "register_operand" "r") (match_operand:QI 2 "register_operand" "r")))] "TARGET_ZBB" - { return TARGET_64BIT ? "rolw\t%0,%1,%2" : "rol\t%0,%1,%2"; } + "rol%~\t%0,%1,%2" [(set_attr "type" "bitmanip")]) (define_insn "rotldi3" diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 38854b42309..3647cae5a42 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -3674,12 +3674,22 @@ riscv_memmodel_needs_release_fence (enum memmodel model) 'i' Print i if the operand is not a register. 'S' Print shift-index of single-bit mask OP. 'T' Print shift-index of inverted single-bit mask OP. + '~' Print w if TARGET_64BIT is true; otherwise not print anything. Note please keep this list and the list in riscv.md in sync. */ static void riscv_print_operand (FILE *file, rtx op, int letter) { + /* `~` does not take an operand so op will be null + Check for before accessing op. + */ + if (letter == '~') + { + if (TARGET_64BIT) + fputc('w', file); + return; + } machine_mode mode = GET_MODE (op); enum rtx_code code = GET_CODE (op); @@ -3755,6 +3765,13 @@ riscv_print_operand (FILE *file, rtx op, int letter) } } +/* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P */ +static bool +riscv_print_operand_punct_valid_p (unsigned char code) +{ + return (code == '~'); +} + /* Implement TARGET_PRINT_OPERAND_ADDRESS. */ static void @@ -5695,6 +5712,8 @@ riscv_asan_shadow_offset (void) #define TARGET_PRINT_OPERAND riscv_print_operand #undef TARGET_PRINT_OPERAND_ADDRESS #define TARGET_PRINT_OPERAND_ADDRESS riscv_print_operand_address +#undef TARGET_PRINT_OPERAND_PUNCT_VALID_P +#define TARGET_PRINT_OPERAND_PUNCT_VALID_P riscv_print_operand_punct_valid_p #undef TARGET_SETUP_INCOMING_VARARGS #define TARGET_SETUP_INCOMING_VARARGS riscv_setup_incoming_varargs diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 5c775040ac3..a5b740a7c35 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -32,6 +32,7 @@ ;; i -- Print i if the operand is not a register. ;; S -- Print shift-index of single-bit mask OP. ;; T -- Print shift-index of inverted single-bit mask OP. +;; ~ -- Print w if TARGET_64BIT is true; otherwise not print anything. (define_c_enum "unspec" [ ;; Override return address for exception handling. @@ -312,7 +313,7 @@ (plus:SI (match_operand:SI 1 "register_operand" " r,r") (match_operand:SI 2 "arith_operand" " r,I")))] "" - { return TARGET_64BIT ? "add%i2w\t%0,%1,%2" : "add%i2\t%0,%1,%2"; } + "add%i2%~\t%0,%1,%2" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -452,7 +453,7 @@ (minus:SI (match_operand:SI 1 "reg_or_0_operand" " rJ") (match_operand:SI 2 "register_operand" " r")))] "" - { return TARGET_64BIT ? "subw\t%0,%z1,%2" : "sub\t%0,%z1,%2"; } + "sub%~\t%0,%z1,%2" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -568,7 +569,7 @@ [(set (match_operand:SI 0 "register_operand" "=r") (neg:SI (match_operand:SI 1 "register_operand" " r")))] "" - { return TARGET_64BIT ? "negw\t%0,%1" : "neg\t%0,%1"; } + "neg%~\t%0,%1" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -613,7 +614,7 @@ (mult:SI (match_operand:SI 1 "register_operand" " r") (match_operand:SI 2 "register_operand" " r")))] "TARGET_MUL" - { return TARGET_64BIT ? "mulw\t%0,%1,%2" : "mul\t%0,%1,%2"; } + "mul%~\t%0,%1,%2" [(set_attr "type" "imul") (set_attr "mode" "SI")]) @@ -883,7 +884,7 @@ (any_div:SI (match_operand:SI 1 "register_operand" " r") (match_operand:SI 2 "register_operand" " r")))] "TARGET_DIV" - { return TARGET_64BIT ? "%i2w\t%0,%1,%2" : "%i2\t%0,%1,%2"; } + "%i2%~\t%0,%1,%2" [(set_attr "type" "idiv") (set_attr "mode" "SI")]) @@ -1539,7 +1540,7 @@ (plus:HI (match_operand:HISI 1 "register_operand" " r,r") (match_operand:HISI 2 "arith_operand" " r,I")))] "" - { return TARGET_64BIT ? "add%i2w\t%0,%1,%2" : "add%i2\t%0,%1,%2"; } + "add%i2%~\t%0,%1,%2" [(set_attr "type" "arith") (set_attr "mode" "HI")]) @@ -1721,7 +1722,7 @@ operands[2] = GEN_INT (INTVAL (operands[2]) & (GET_MODE_BITSIZE (SImode) - 1)); - return TARGET_64BIT ? "%i2w\t%0,%1,%2" : "%i2\t%0,%1,%2"; + return "%i2%~\t%0,%1,%2"; } [(set_attr "type" "shift") (set_attr "mode" "SI")])