From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1314) id 9D9003858413; Mon, 15 Aug 2022 23:14:14 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 9D9003858413 Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Andrew Pinski To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/pinskia/heads/riscvbit)] Use constraints/predicates instead of checking const_int directly for shNadd patterns X-Act-Checkin: gcc X-Git-Author: Andrew Pinski X-Git-Refname: refs/users/pinskia/heads/riscvbit X-Git-Oldrev: 8e4eee491862ce843af945d590063832ee2f2906 X-Git-Newrev: fffc0b2b786c4c5b572dc756988a7337a8359e18 Message-Id: <20220815231414.9D9003858413@sourceware.org> Date: Mon, 15 Aug 2022 23:14:14 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 15 Aug 2022 23:14:14 -0000 https://gcc.gnu.org/g:fffc0b2b786c4c5b572dc756988a7337a8359e18 commit fffc0b2b786c4c5b572dc756988a7337a8359e18 Author: Andrew Pinski Date: Mon Aug 15 17:50:50 2022 +0000 Use constraints/predicates instead of checking const_int directly for shNadd patterns This simplifies the code and it also fixes other issues dealing with register allocator and many more. gcc/ChangeLog: * config/riscv/bitmanip.md: * config/riscv/constraints.md (Ds3): * config/riscv/predicates.md (imm123_operand): Signed-off-by: Andrew Pinski Change-Id: I278edc4a952ab17227f2eae10431491e278c5713 Diff: --- gcc/config/riscv/bitmanip.md | 8 +++----- gcc/config/riscv/constraints.md | 6 ++++++ gcc/config/riscv/predicates.md | 5 +++++ 3 files changed, 14 insertions(+), 5 deletions(-) diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index ebd6eee1a22..73a36f7751b 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -32,10 +32,9 @@ (define_insn "*shNadd" [(set (match_operand:X 0 "register_operand" "=r") (plus:X (ashift:X (match_operand:X 1 "register_operand" "r") - (match_operand:QI 2 "immediate_operand" "I")) + (match_operand:QI 2 "imm123_operand" "Ds3")) (match_operand:X 3 "register_operand" "r")))] - "TARGET_ZBA - && (INTVAL (operands[2]) >= 1) && (INTVAL (operands[2]) <= 3)" + "TARGET_ZBA" "sh%2add\t%0,%1,%3" [(set_attr "type" "bitmanip") (set_attr "mode" "")]) @@ -44,11 +43,10 @@ [(set (match_operand:DI 0 "register_operand" "=r") (plus:DI (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r") - (match_operand:QI 2 "immediate_operand" "I")) + (match_operand:QI 2 "imm123_operand" "Ds3")) (match_operand 3 "immediate_operand" "")) (match_operand:DI 4 "register_operand" "r")))] "TARGET_64BIT && TARGET_ZBA - && (INTVAL (operands[2]) >= 1) && (INTVAL (operands[2]) <= 3) && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff" "sh%2add.uw\t%0,%1,%4" [(set_attr "type" "bitmanip") diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md index bafa4188ccb..61b84875fd9 100644 --- a/gcc/config/riscv/constraints.md +++ b/gcc/config/riscv/constraints.md @@ -54,6 +54,12 @@ (and (match_code "const_int") (match_test "LUI_OPERAND (ival)"))) +(define_constraint "Ds3" + "@internal + 1, 2 or 3 immediate" + (and (match_code "const_int") + (match_test "IN_RANGE (ival, 1, 3)"))) + ;; Floating-point constant +0.0, used for FCVT-based moves when FMV is ;; not available in RV32. (define_constraint "G" diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index e98db2cb574..77f7ca57209 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -244,6 +244,11 @@ (and (match_code "const_int") (match_test "INTVAL (op) < 5"))) +;; A const_int for sh1add/sh2add/sh3add +(define_predicate "imm123_operand" + (and (match_code "const_int") + (match_test "IN_RANGE (INTVAL (op), 1, 3)"))) + ;; A CONST_INT operand that consists of a single run of consecutive set bits. (define_predicate "consecutive_bits_operand" (match_code "const_int")