From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1314) id 2FD02385087A; Wed, 24 Aug 2022 18:31:25 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 2FD02385087A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1661365885; bh=+5tRoJuFCFjVOtXS8KVR3GIwY/guiP15cSg6/oATV9A=; h=From:To:Subject:Date:From; b=nw8V6gEXVm5II29ZqmtKe5VgbvxmbCU77zFvD0bY3MOPGEVT6zG3z485XVsfQyk1X T8g/kml+AYWkbVCmf3Ci2fWRfR+j57E+wrZZGwa6AF3UAMIXOqZVJe5eG3FW10odI8 HNbb7FrJzyIFOc2qB2JpseiswENB9NceW5pVTsB4= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Andrew Pinski To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-2179] Fix PR 106601: __builtin_bswap16 code gen could be improved with ZBB enabled X-Act-Checkin: gcc X-Git-Author: Andrew Pinski X-Git-Refname: refs/heads/trunk X-Git-Oldrev: cb2daf5acce003300ee948a89860c0d13ebcae79 X-Git-Newrev: e5e6983c3da53729e58a32af1d531ea74b3dbf5d Message-Id: <20220824183125.2FD02385087A@sourceware.org> Date: Wed, 24 Aug 2022 18:31:25 +0000 (GMT) List-Id: https://gcc.gnu.org/g:e5e6983c3da53729e58a32af1d531ea74b3dbf5d commit r13-2179-ge5e6983c3da53729e58a32af1d531ea74b3dbf5d Author: Andrew Pinski Date: Fri Aug 19 17:46:40 2022 +0000 Fix PR 106601: __builtin_bswap16 code gen could be improved with ZBB enabled The default expansion for bswap16 is two extractions (shift/and) followed by an insertation (ior) and then a zero extend. This can be improved with ZBB enabled to just full byteswap followed by a (logical) shift right. This patch adds a new pattern for this which does that. OK? Built and tested on riscv32-linux-gnu and riscv64-linux-gnu. gcc/ChangeLog: PR target/106601 * config/riscv/bitmanip.md (bswaphi2): New pattern. gcc/testsuite/ChangeLog: PR target/106601 * gcc.target/riscv/zbb_32_bswap-2.c: New test. * gcc.target/riscv/zbb_bswap-2.c: New test. Diff: --- gcc/config/riscv/bitmanip.md | 24 ++++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/zbb_32_bswap-2.c | 12 ++++++++++++ gcc/testsuite/gcc.target/riscv/zbb_bswap-2.c | 12 ++++++++++++ 3 files changed, 48 insertions(+) diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index c7ba667f87a..c4383285d81 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -276,6 +276,30 @@ "rev8\t%0,%1" [(set_attr "type" "bitmanip")]) +;; HI bswap can be emulated using SI/DI bswap followed +;; by a logical shift right +;; SI bswap for TARGET_64BIT is already similarly in +;; the common code. +(define_expand "bswaphi2" + [(set (match_operand:HI 0 "register_operand" "=r") + (bswap:HI (match_operand:HI 1 "register_operand" "r")))] + "TARGET_ZBB" +{ + rtx tmp = gen_reg_rtx (word_mode); + rtx newop1 = gen_lowpart (word_mode, operands[1]); + if (TARGET_64BIT) + emit_insn (gen_bswapdi2 (tmp, newop1)); + else + emit_insn (gen_bswapsi2 (tmp, newop1)); + rtx tmp1 = gen_reg_rtx (word_mode); + if (TARGET_64BIT) + emit_insn (gen_lshrdi3 (tmp1, tmp, GEN_INT (64 - 16))); + else + emit_insn (gen_lshrsi3 (tmp1, tmp, GEN_INT (32 - 16))); + emit_move_insn (operands[0], gen_lowpart (HImode, tmp1)); + DONE; +}) + (define_insn "3" [(set (match_operand:X 0 "register_operand" "=r") (bitmanip_minmax:X (match_operand:X 1 "register_operand" "r") diff --git a/gcc/testsuite/gcc.target/riscv/zbb_32_bswap-2.c b/gcc/testsuite/gcc.target/riscv/zbb_32_bswap-2.c new file mode 100644 index 00000000000..679b34c4e41 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zbb_32_bswap-2.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zbb -mabi=ilp32" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +int foo(int n) +{ + return __builtin_bswap16(n); +} + +/* { dg-final { scan-assembler "rev8" } } */ +/* { dg-final { scan-assembler "srli" } } */ + diff --git a/gcc/testsuite/gcc.target/riscv/zbb_bswap-2.c b/gcc/testsuite/gcc.target/riscv/zbb_bswap-2.c new file mode 100644 index 00000000000..c358f6683f3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zbb_bswap-2.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zbb -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +int foo(int n) +{ + return __builtin_bswap16(n); +} + +/* { dg-final { scan-assembler "rev8" } } */ +/* { dg-final { scan-assembler "srli" } } */ +