From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1314) id B1FD03852741; Wed, 24 Aug 2022 19:20:18 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org B1FD03852741 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1661368818; bh=FkahLpfTM1pcEHxzhfImq+01Oasz4cXZOG22QWkYC1o=; h=From:To:Subject:Date:From; b=eh5ZwTYPSCcCvG6HbPmotGzkyZzxFI5+7xIknzE1G7AYLxxqF7n6hpLSStTxrS6PP RP/p9Np+fxEzICLEyrZLnEZ/O/eby6acNrrGvPTECTorwNHMx6DbZhr6N5GcDVzXsN QMuLDcBDJCaDB8HNRFXfNXuHn05PbAixzt6EfnKs= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Andrew Pinski To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-2184] [RISCV] Add the list of operand modifiers to riscv.md too X-Act-Checkin: gcc X-Git-Author: Andrew Pinski X-Git-Refname: refs/heads/trunk X-Git-Oldrev: 7770e0ad8f4bcd2c7852fa88eb7d5235f68a811d X-Git-Newrev: 380b8fd96e10c45ce8470b906037cf487ac3f91f Message-Id: <20220824192018.B1FD03852741@sourceware.org> Date: Wed, 24 Aug 2022 19:20:18 +0000 (GMT) List-Id: https://gcc.gnu.org/g:380b8fd96e10c45ce8470b906037cf487ac3f91f commit r13-2184-g380b8fd96e10c45ce8470b906037cf487ac3f91f Author: Andrew Pinski Date: Fri Aug 12 17:19:36 2022 +0000 [RISCV] Add the list of operand modifiers to riscv.md too To make it easier to find operands modifiers while in the md file, add the list of modifiers to the top of the md file. This is similar to i386 target. OK? Built and tested for riscv32-linux-gnu and riscv64-linux-gnu. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_print_operand): Make a mention to keep the list in riscv.md in sync with this list. * config/riscv/riscv.md: Add list of modifiers as comments. Diff: --- gcc/config/riscv/riscv.cc | 4 +++- gcc/config/riscv/riscv.md | 14 ++++++++++++++ 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 7c120eaa8e3..189be5e4e6f 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -3730,7 +3730,9 @@ riscv_memmodel_needs_release_fence (enum memmodel model) 'z' Print x0 if OP is zero, otherwise print OP normally. 'i' Print i if the operand is not a register. 'S' Print shift-index of single-bit mask OP. - 'T' Print shift-index of inverted single-bit mask OP. */ + 'T' Print shift-index of inverted single-bit mask OP. + + Note please keep this list and the list in riscv.md in sync. */ static void riscv_print_operand (FILE *file, rtx op, int letter) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 8edb3859aab..aad2836d179 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -19,6 +19,20 @@ ;; along with GCC; see the file COPYING3. If not see ;; . + +;; Keep this list and the one above riscv_print_operand in sync. +;; The special asm out single letter directives following a '%' are: +;; h -- Print the high-part relocation associated with OP, after stripping +;; any outermost HIGH. +;; R -- Print the low-part relocation associated with OP. +;; C -- Print the integer branch condition for comparison OP. +;; A -- Print the atomic operation suffix for memory model OP. +;; F -- Print a FENCE if the memory model requires a release. +;; z -- Print x0 if OP is zero, otherwise print OP normally. +;; i -- Print i if the operand is not a register. +;; S -- Print shift-index of single-bit mask OP. +;; T -- Print shift-index of inverted single-bit mask OP. + (define_c_enum "unspec" [ ;; Override return address for exception handling. UNSPEC_EH_RETURN