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From: Andrew Pinski <pinskia@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-2185] [RISCV] Add %~ to print w if TARGET_64BIT and use it Date: Wed, 24 Aug 2022 19:20:23 +0000 (GMT) [thread overview] Message-ID: <20220824192023.CB73F3852776@sourceware.org> (raw) https://gcc.gnu.org/g:473d7aad848fe6ec151e7445e06c6e06ee4bd576 commit r13-2185-g473d7aad848fe6ec151e7445e06c6e06ee4bd576 Author: Andrew Pinski <apinski@marvell.com> Date: Fri Aug 12 17:46:16 2022 +0000 [RISCV] Add %~ to print w if TARGET_64BIT and use it To make things easier and more maintainable, we need to add support printing out w if TARGET_64BIT so this patch adds %~ to do that, similar how the x86 backend uses %~ to print out i/f for TARGET_AVX2. We could have chosen any punctuation symbol but ~ looks the closest to w. OK? Build and tested for riscv64-linux-gnu and riscv32-linux-gnu with no regressions. Thanks, Andrew Pinski gcc/ChangeLog: * config/riscv/riscv.cc (riscv_print_operand): Handle '~'. (riscv_print_operand_punct_valid_p): New function (TARGET_PRINT_OPERAND_PUNCT_VALID_P): Define. * config/riscv/bitmanip.md (<bitmanip_optab>si2/clz_ctz_pcnt): Use %~ instead of conditional the pattern on TARGET_64BIT. (rotrsi3): Likewise. (rotlsi3): Likewise. * config/riscv/riscv.md: Add ~ to the list of modifiers. (addsi3): Use %~ instead of conditional the pattern on TARGET_64BIT. (subsi3): Likewise. (negsi2): Likewise. (mulsi3): Likewise. (optab>si3/any_div): Likewise. (*add<mode>hi3): Likewise. (<optab>si3/any_shift): Likewise. Diff: --- gcc/config/riscv/bitmanip.md | 6 +++--- gcc/config/riscv/riscv.cc | 19 +++++++++++++++++++ gcc/config/riscv/riscv.md | 15 ++++++++------- 3 files changed, 30 insertions(+), 10 deletions(-) diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index 6317fedbbf6..9f3c306423d 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -143,7 +143,7 @@ [(set (match_operand:SI 0 "register_operand" "=r") (clz_ctz_pcnt:SI (match_operand:SI 1 "register_operand" "r")))] "TARGET_ZBB" - { return TARGET_64BIT ? "<bitmanip_insn>w\t%0,%1" : "<bitmanip_insn>\t%0,%1"; } + "<bitmanip_insn>%~\t%0,%1" [(set_attr "type" "bitmanip") (set_attr "mode" "SI")]) @@ -201,7 +201,7 @@ (rotatert:SI (match_operand:SI 1 "register_operand" "r") (match_operand:QI 2 "arith_operand" "rI")))] "TARGET_ZBB" - { return TARGET_64BIT ? "ror%i2w\t%0,%1,%2" : "ror%i2\t%0,%1,%2"; } + "ror%i2%~\t%0,%1,%2" [(set_attr "type" "bitmanip")]) (define_insn "rotrdi3" @@ -225,7 +225,7 @@ (rotate:SI (match_operand:SI 1 "register_operand" "r") (match_operand:QI 2 "register_operand" "r")))] "TARGET_ZBB" - { return TARGET_64BIT ? "rolw\t%0,%1,%2" : "rol\t%0,%1,%2"; } + "rol%~\t%0,%1,%2" [(set_attr "type" "bitmanip")]) (define_insn "rotldi3" diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 189be5e4e6f..22d0f6d604c 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -3731,12 +3731,22 @@ riscv_memmodel_needs_release_fence (enum memmodel model) 'i' Print i if the operand is not a register. 'S' Print shift-index of single-bit mask OP. 'T' Print shift-index of inverted single-bit mask OP. + '~' Print w if TARGET_64BIT is true; otherwise not print anything. Note please keep this list and the list in riscv.md in sync. */ static void riscv_print_operand (FILE *file, rtx op, int letter) { + /* `~` does not take an operand so op will be null + Check for before accessing op. + */ + if (letter == '~') + { + if (TARGET_64BIT) + fputc('w', file); + return; + } machine_mode mode = GET_MODE (op); enum rtx_code code = GET_CODE (op); @@ -3812,6 +3822,13 @@ riscv_print_operand (FILE *file, rtx op, int letter) } } +/* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P */ +static bool +riscv_print_operand_punct_valid_p (unsigned char code) +{ + return (code == '~'); +} + /* Implement TARGET_PRINT_OPERAND_ADDRESS. */ static void @@ -5900,6 +5917,8 @@ riscv_init_libfuncs (void) #define TARGET_PRINT_OPERAND riscv_print_operand #undef TARGET_PRINT_OPERAND_ADDRESS #define TARGET_PRINT_OPERAND_ADDRESS riscv_print_operand_address +#undef TARGET_PRINT_OPERAND_PUNCT_VALID_P +#define TARGET_PRINT_OPERAND_PUNCT_VALID_P riscv_print_operand_punct_valid_p #undef TARGET_SETUP_INCOMING_VARARGS #define TARGET_SETUP_INCOMING_VARARGS riscv_setup_incoming_varargs diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index aad2836d179..30cd07dc6f5 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -32,6 +32,7 @@ ;; i -- Print i if the operand is not a register. ;; S -- Print shift-index of single-bit mask OP. ;; T -- Print shift-index of inverted single-bit mask OP. +;; ~ -- Print w if TARGET_64BIT is true; otherwise not print anything. (define_c_enum "unspec" [ ;; Override return address for exception handling. @@ -312,7 +313,7 @@ (plus:SI (match_operand:SI 1 "register_operand" " r,r") (match_operand:SI 2 "arith_operand" " r,I")))] "" - { return TARGET_64BIT ? "add%i2w\t%0,%1,%2" : "add%i2\t%0,%1,%2"; } + "add%i2%~\t%0,%1,%2" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -452,7 +453,7 @@ (minus:SI (match_operand:SI 1 "reg_or_0_operand" " rJ") (match_operand:SI 2 "register_operand" " r")))] "" - { return TARGET_64BIT ? "subw\t%0,%z1,%2" : "sub\t%0,%z1,%2"; } + "sub%~\t%0,%z1,%2" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -568,7 +569,7 @@ [(set (match_operand:SI 0 "register_operand" "=r") (neg:SI (match_operand:SI 1 "register_operand" " r")))] "" - { return TARGET_64BIT ? "negw\t%0,%1" : "neg\t%0,%1"; } + "neg%~\t%0,%1" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -613,7 +614,7 @@ (mult:SI (match_operand:SI 1 "register_operand" " r") (match_operand:SI 2 "register_operand" " r")))] "TARGET_MUL" - { return TARGET_64BIT ? "mulw\t%0,%1,%2" : "mul\t%0,%1,%2"; } + "mul%~\t%0,%1,%2" [(set_attr "type" "imul") (set_attr "mode" "SI")]) @@ -883,7 +884,7 @@ (any_div:SI (match_operand:SI 1 "register_operand" " r") (match_operand:SI 2 "register_operand" " r")))] "TARGET_DIV" - { return TARGET_64BIT ? "<insn>%i2w\t%0,%1,%2" : "<insn>%i2\t%0,%1,%2"; } + "<insn>%i2%~\t%0,%1,%2" [(set_attr "type" "idiv") (set_attr "mode" "SI")]) @@ -1605,7 +1606,7 @@ (plus:HI (match_operand:HISI 1 "register_operand" " r,r") (match_operand:HISI 2 "arith_operand" " r,I")))] "" - { return TARGET_64BIT ? "add%i2w\t%0,%1,%2" : "add%i2\t%0,%1,%2"; } + "add%i2%~\t%0,%1,%2" [(set_attr "type" "arith") (set_attr "mode" "HI")]) @@ -1787,7 +1788,7 @@ operands[2] = GEN_INT (INTVAL (operands[2]) & (GET_MODE_BITSIZE (SImode) - 1)); - return TARGET_64BIT ? "<insn>%i2w\t%0,%1,%2" : "<insn>%i2\t%0,%1,%2"; + return "<insn>%i2%~\t%0,%1,%2"; } [(set_attr "type" "shift") (set_attr "mode" "SI")])
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