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From: Andrew Pinski <pinskia@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-2187] [RISCV] Use a constraint for bset<mode>_mask and bset<mode>_1_mask Date: Wed, 24 Aug 2022 19:20:34 +0000 (GMT) [thread overview] Message-ID: <20220824192034.107FF385482A@sourceware.org> (raw) https://gcc.gnu.org/g:95989ab39bbedd34e6f508de3109cb5c17db433e commit r13-2187-g95989ab39bbedd34e6f508de3109cb5c17db433e Author: Andrew Pinski <apinski@marvell.com> Date: Mon Aug 15 18:39:17 2022 +0000 [RISCV] Use a constraint for bset<mode>_mask and bset<mode>_1_mask A constraint here just makes it easier to understand what the operands are. OK? Built and tested on riscv32-linux-gnu and riscv64-linux-gnu with --with-arch=rvNimafdc_zba_zbb_zbc_zbs (where N is 32 and 64). Thanks, Andrew Pinski gcc/ChangeLog: * config/riscv/constraints.md (DsS): New constraint. (DsD): New constraint. * config/riscv/iterators.md (shiftm1c): New iterator. * config/riscv/bitmanip.md (*bset<mode>_mask): Use shiftm1c. (*bset<mode>_1_mask): Likewise. Diff: --- gcc/config/riscv/bitmanip.md | 4 ++-- gcc/config/riscv/constraints.md | 12 ++++++++++++ gcc/config/riscv/iterators.md | 1 + 3 files changed, 15 insertions(+), 2 deletions(-) diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index 258bd5a84fc..73b2c1040b6 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -297,7 +297,7 @@ (ior:X (ashift:X (const_int 1) (subreg:QI (and:X (match_operand:X 2 "register_operand" "r") - (match_operand 3 "<X:shiftm1>" "i")) 0)) + (match_operand 3 "<X:shiftm1>" "<X:shiftm1p>")) 0)) (match_operand:X 1 "register_operand" "r")))] "TARGET_ZBS" "bset\t%0,%1,%2" @@ -316,7 +316,7 @@ (ashift:X (const_int 1) (subreg:QI (and:X (match_operand:X 1 "register_operand" "r") - (match_operand 2 "<X:shiftm1>" "i")) 0)))] + (match_operand 2 "<X:shiftm1>" "<X:shiftm1p>")) 0)))] "TARGET_ZBS" "bset\t%0,x0,%1" [(set_attr "type" "bitmanip")]) diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md index 61b84875fd9..444870ad060 100644 --- a/gcc/config/riscv/constraints.md +++ b/gcc/config/riscv/constraints.md @@ -60,6 +60,18 @@ (and (match_code "const_int") (match_test "IN_RANGE (ival, 1, 3)"))) +(define_constraint "DsS" + "@internal + 31 immediate" + (and (match_code "const_int") + (match_test "ival == 31"))) + +(define_constraint "DsD" + "@internal + 63 immediate" + (and (match_code "const_int") + (match_test "ival == 63"))) + ;; Floating-point constant +0.0, used for FCVT-based moves when FMV is ;; not available in RV32. (define_constraint "G" diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md index 2d7223d8a8a..39dffabc235 100644 --- a/gcc/config/riscv/iterators.md +++ b/gcc/config/riscv/iterators.md @@ -114,6 +114,7 @@ ; bitmanip mode attribute (define_mode_attr shiftm1 [(SI "const31_operand") (DI "const63_operand")]) +(define_mode_attr shiftm1p [(SI "DsS") (DI "DsD")]) ;; ------------------------------------------------------------------- ;; Code Iterators
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