From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2017) id 4A27B3857B93; Mon, 29 Aug 2022 09:17:59 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 4A27B3857B93 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1661764679; bh=WNGIFtVSvcYdMXiS94Pjl9o2X+Q0RTS90t/sOh7c4nw=; h=From:To:Subject:Date:From; b=fTXL5/wiq4Nr1qcRfTnZUT1+xgjz1kMNB8QCg2TqTO7vN47xMHwaK1EMb31sIBrpV PLkyy2UDyNLFqU5IKvcdW/VH7jA54SrKcKWZzAQ9H118eO4xLpS4yHkbNFkRVZ1VXt hdMGPa50w7Tj5GRpnTEAOcbLUakqB+EoWk3Qu9ao= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Robin Dapp To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-2248] s390: Use vpdi and verllg in vec_reve. X-Act-Checkin: gcc X-Git-Author: Robin Dapp X-Git-Refname: refs/heads/master X-Git-Oldrev: c2f4a1b7d104427165f609bac830bb59504ec99e X-Git-Newrev: 8cdebe087619329facf19ba849d4d489a9a933e2 Message-Id: <20220829091759.4A27B3857B93@sourceware.org> Date: Mon, 29 Aug 2022 09:17:59 +0000 (GMT) List-Id: https://gcc.gnu.org/g:8cdebe087619329facf19ba849d4d489a9a933e2 commit r13-2248-g8cdebe087619329facf19ba849d4d489a9a933e2 Author: Robin Dapp Date: Fri Jun 24 15:15:14 2022 +0200 s390: Use vpdi and verllg in vec_reve. Swapping the two elements of a V2DImode or V2DFmode vector can be done with vpdi instead of using the generic way of loading a permutation mask from the literal pool and vperm. Analogous to the V2DI/V2DF case reversing the elements of a four-element vector can be done by first swapping the elements of the first doubleword as well the ones of the second one and subsequently rotate the doublewords by 32 bits. gcc/ChangeLog: PR target/100869 * config/s390/vector.md (@vpdi4_2): New pattern. (rotl3_di): New pattern. * config/s390/vx-builtins.md: Use vpdi and verll for reversing elements. gcc/testsuite/ChangeLog: * gcc.target/s390/zvector/vec-reve-int-long.c: New test. Diff: --- gcc/config/s390/vector.md | 28 +++++++++++++++ gcc/config/s390/vx-builtins.md | 41 ++++++++++++++++++++++ .../gcc.target/s390/zvector/vec-reve-int-long.c | 31 ++++++++++++++++ 3 files changed, 100 insertions(+) diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md index 624729814af..b6a3da6dd0a 100644 --- a/gcc/config/s390/vector.md +++ b/gcc/config/s390/vector.md @@ -797,6 +797,17 @@ "vpdi\t%v0,%v1,%v2,4" [(set_attr "op_type" "VRR")]) +; Second DW of op1 and first DW of op2 (when interpreted as 2-element vector). +(define_insn "@vpdi4_2" + [(set (match_operand:V_HW_4 0 "register_operand" "=v") + (vec_select:V_HW_4 + (vec_concat: + (match_operand:V_HW_4 1 "register_operand" "v") + (match_operand:V_HW_4 2 "register_operand" "v")) + (parallel [(const_int 2) (const_int 3) (const_int 4) (const_int 5)])))] + "TARGET_VX" + "vpdi\t%v0,%v1,%v2,4" + [(set_attr "op_type" "VRR")]) (define_insn "*vmrhb" [(set (match_operand:V16QI 0 "register_operand" "=v") @@ -1255,6 +1266,23 @@ "\t%v0,%v1,%Y2" [(set_attr "op_type" "VRS")]) +; verllg for V4SI/V4SF. This swaps the first and the second two +; elements of a vector and is only valid in that context. +(define_expand "rotl3_di" + [ + (set (match_dup 2) + (subreg:V2DI (match_operand:V_HW_4 1) 0)) + (set (match_dup 3) + (rotate:V2DI + (match_dup 2) + (const_int 32))) + (set (match_operand:V_HW_4 0) + (subreg:V_HW_4 (match_dup 3) 0))] + "TARGET_VX" + { + operands[2] = gen_reg_rtx (V2DImode); + operands[3] = gen_reg_rtx (V2DImode); + }) ; Shift each element by corresponding vector element diff --git a/gcc/config/s390/vx-builtins.md b/gcc/config/s390/vx-builtins.md index 98ee08b2683..69ce00b5efa 100644 --- a/gcc/config/s390/vx-builtins.md +++ b/gcc/config/s390/vx-builtins.md @@ -2181,6 +2181,47 @@ vster\t%v1,%v0" [(set_attr "op_type" "*,VRX,VRX")]) +; Swapping v2df/v2di can be done via vpdi on z13 and z14. +(define_split + [(set (match_operand:V_HW_2 0 "register_operand" "") + (unspec:V_HW_2 [(match_operand:V_HW_2 1 "register_operand" "")] + UNSPEC_VEC_ELTSWAP))] + "TARGET_VX && can_create_pseudo_p ()" + [(set (match_operand:V_HW_2 0 "register_operand" "=v") + (vec_select:V_HW_2 + (vec_concat: + (match_operand:V_HW_2 1 "register_operand" "v") + (match_dup 1)) + (parallel [(const_int 1) (const_int 2)])))] +) + + +; Swapping v4df/v4si can be done via vpdi and rot. +(define_split + [(set (match_operand:V_HW_4 0 "register_operand" "") + (unspec:V_HW_4 [(match_operand:V_HW_4 1 "register_operand" "")] + UNSPEC_VEC_ELTSWAP))] + "TARGET_VX && can_create_pseudo_p ()" + [(set (match_dup 2) + (vec_select:V_HW_4 + (vec_concat: + (match_dup 1) + (match_dup 1)) + (parallel [(const_int 2) (const_int 3) (const_int 4) (const_int 5)]))) + (set (match_dup 3) + (subreg:V2DI (match_dup 2) 0)) + (set (match_dup 4) + (rotate:V2DI + (match_dup 3) + (const_int 32))) + (set (match_operand:V_HW_4 0) + (subreg:V_HW_4 (match_dup 4) 0))] +{ + operands[2] = gen_reg_rtx (mode); + operands[3] = gen_reg_rtx (V2DImode); + operands[4] = gen_reg_rtx (V2DImode); +}) + ; z15 has instructions for doing element reversal from mem to reg ; or the other way around. For reg to reg or on pre z15 machines ; we have to emulate it with vector permute. diff --git a/gcc/testsuite/gcc.target/s390/zvector/vec-reve-int-long.c b/gcc/testsuite/gcc.target/s390/zvector/vec-reve-int-long.c new file mode 100644 index 00000000000..dff3a94066c --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/vec-reve-int-long.c @@ -0,0 +1,31 @@ +/* Test that we use vpdi in order to reverse vectors + with two elements instead of creating a literal-pool entry + and permuting with vperm. */ +/* { dg-do compile { target { s390*-*-* } } } */ +/* { dg-options "-O2 -march=z14 -mzarch -mzvector -fno-unroll-loops" } */ + +/* { dg-final { scan-assembler-times "vpdi\t" 4 } } */ +/* { dg-final { scan-assembler-times "verllg\t" 2 } } */ +/* { dg-final { scan-assembler-times "vperm" 0 } } */ + +#include + +vector double reved (vector double a) +{ + return vec_reve (a); +} + +vector long long revel (vector long long a) +{ + return vec_reve (a); +} + +vector float revef (vector float a) +{ + return vec_reve (a); +} + +vector int revei (vector int a) +{ + return vec_reve (a); +}