From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2017) id 10F09385740D; Mon, 29 Aug 2022 09:18:05 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 10F09385740D DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1661764685; bh=ESj3N4vHqan6mltpp3CK4rBL06LHJbY8uH7XXAD9EGQ=; h=From:To:Subject:Date:From; b=jB2WAg6dAyV+3Np2jgZ7IXy354GQlM2qUAWibHTRpUmbupcAf/hITKUNW7mzQIYq4 Cu/X/JkGba5ZoWqDO+0PvC4TJeiDAv+n+krXu5xVgewHQE41zmXw8ox0Ksa1jos8YR 5BgPAgoVsvWd+87rvtlZM5MA5pyJxWFiflENUeW0= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Robin Dapp To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-2249] s390: Implement vec_extract via vec_select. X-Act-Checkin: gcc X-Git-Author: Robin Dapp X-Git-Refname: refs/heads/master X-Git-Oldrev: 8cdebe087619329facf19ba849d4d489a9a933e2 X-Git-Newrev: bde28df1933b972e080613a00b6819413aefa2e6 Message-Id: <20220829091805.10F09385740D@sourceware.org> Date: Mon, 29 Aug 2022 09:18:05 +0000 (GMT) List-Id: https://gcc.gnu.org/g:bde28df1933b972e080613a00b6819413aefa2e6 commit r13-2249-gbde28df1933b972e080613a00b6819413aefa2e6 Author: Robin Dapp Date: Mon Jul 4 14:19:29 2022 +0200 s390: Implement vec_extract via vec_select. vec_select can handle dynamic/runtime masks nowadays. Therefore we can get rid of the UNSPEC_VEC_EXTRACT that was preventing further optimizations like combining instructions with vec_extract patterns. gcc/ChangeLog: * config/s390/s390.md: Remove UNSPEC_VEC_EXTRACT. * config/s390/vector.md: Rewrite patterns to use vec_select. * config/s390/vx-builtins.md (vec_scatter_element_SI): Likewise. Diff: --- gcc/config/s390/s390.md | 5 ++-- gcc/config/s390/vector.md | 46 ++++++++++++++++-------------- gcc/config/s390/vx-builtins.md | 63 +++++++++++++++++++++++------------------- 3 files changed, 61 insertions(+), 53 deletions(-) diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index aaa247d7612..962927c3112 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -153,7 +153,6 @@ UNSPEC_VEC_VMALO UNSPEC_VEC_GATHER - UNSPEC_VEC_EXTRACT UNSPEC_VEC_INSERT_AND_ZERO UNSPEC_VEC_LOAD_BNDRY UNSPEC_VEC_LOAD_LEN @@ -1744,8 +1743,8 @@ && GENERAL_REG_P (operands[0]) && VECTOR_REG_P (operands[1])" [(set (match_dup 2) (match_dup 4)) - (set (match_dup 3) (unspec:DI [(match_dup 5) (const_int 1)] - UNSPEC_VEC_EXTRACT))] + (set (match_dup 3) (vec_select:DI (match_dup 5) + (parallel [(const_int 1)])))] { operands[2] = operand_subword (operands[0], 0, 0, TImode); operands[3] = operand_subword (operands[0], 1, 0, TImode); diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md index b6a3da6dd0a..dde74afc869 100644 --- a/gcc/config/s390/vector.md +++ b/gcc/config/s390/vector.md @@ -270,11 +270,13 @@ (match_operand:V_128 1 "register_operand" ""))] "TARGET_VX && GENERAL_REG_P (operands[0]) && VECTOR_REG_P (operands[1])" [(set (match_dup 2) - (unspec:DI [(subreg:V2DI (match_dup 1) 0) - (const_int 0)] UNSPEC_VEC_EXTRACT)) + (vec_select:DI + (subreg:V2DI (match_dup 1) 0) + (parallel [(const_int 0)]))) (set (match_dup 3) - (unspec:DI [(subreg:V2DI (match_dup 1) 0) - (const_int 1)] UNSPEC_VEC_EXTRACT))] + (vec_select:DI + (subreg:V2DI (match_dup 1) 0) + (parallel [(const_int 1)])))] { operands[2] = operand_subword (operands[0], 0, 0, mode); operands[3] = operand_subword (operands[0], 1, 0, mode); @@ -511,22 +513,24 @@ [(set_attr "op_type" "VRS")]) -; FIXME: Support also vector mode operands for 0 -; FIXME: This should be (vec_select ..) or something but it does only allow constant selectors :( -; This is used via RTL standard name as well as for expanding the builtin +;; FIXME: Support also vector mode operands for 0 +;; This is used via RTL standard name as well as for expanding the builtin (define_expand "vec_extract" - [(set (match_operand: 0 "nonimmediate_operand" "") - (unspec: [(match_operand:V 1 "register_operand" "") - (match_operand:SI 2 "nonmemory_operand" "")] - UNSPEC_VEC_EXTRACT))] - "TARGET_VX") + [(set (match_operand: 0 "nonimmediate_operand" "") + (vec_select: + (match_operand:V 1 "register_operand" "") + (parallel + [(match_operand:SI 2 "nonmemory_operand" "")])))] + "TARGET_VX" +) ; vlgvb, vlgvh, vlgvf, vlgvg, vsteb, vsteh, vstef, vsteg (define_insn "*vec_extract" - [(set (match_operand: 0 "nonimmediate_operand" "=d,R") - (unspec: [(match_operand:V 1 "register_operand" "v,v") - (match_operand:SI 2 "nonmemory_operand" "an,I")] - UNSPEC_VEC_EXTRACT))] + [(set (match_operand: 0 "nonimmediate_operand" "=d,R") + (vec_select: + (match_operand:V 1 "nonmemory_operand" "v,v") + (parallel + [(match_operand:SI 2 "nonmemory_operand" "an,I")])))] "TARGET_VX && (!CONST_INT_P (operands[2]) || UINTVAL (operands[2]) < GET_MODE_NUNITS (mode))" @@ -537,11 +541,11 @@ ; vlgvb, vlgvh, vlgvf, vlgvg (define_insn "*vec_extract_plus" - [(set (match_operand: 0 "nonimmediate_operand" "=d") - (unspec: [(match_operand:V 1 "register_operand" "v") - (plus:SI (match_operand:SI 2 "nonmemory_operand" "a") - (match_operand:SI 3 "const_int_operand" "n"))] - UNSPEC_VEC_EXTRACT))] + [(set (match_operand: 0 "nonimmediate_operand" "=d") + (vec_select: + (match_operand:V 1 "register_operand" "v") + (plus:SI (match_operand:SI 2 "nonmemory_operand" "a") + (parallel [(match_operand:SI 3 "const_int_operand" "n")]))))] "TARGET_VX" "vlgv\t%0,%v1,%Y3(%2)" [(set_attr "op_type" "VRS")]) diff --git a/gcc/config/s390/vx-builtins.md b/gcc/config/s390/vx-builtins.md index 69ce00b5efa..d20771dbe8a 100644 --- a/gcc/config/s390/vx-builtins.md +++ b/gcc/config/s390/vx-builtins.md @@ -440,12 +440,13 @@ (define_insn "vec_scatter_element_DI" [(set (mem: (plus:DI (zero_extend:DI - (unspec:SI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:QI 3 "const_mask_operand" "C")] - UNSPEC_VEC_EXTRACT)) - (match_operand:SI 2 "address_operand" "ZQ"))) - (unspec: [(match_operand:V_HW_4 0 "register_operand" "v") - (match_dup 3)] UNSPEC_VEC_EXTRACT))] + (vec_select:SI + (match_operand:V4SI 1 "register_operand" "v") + (parallel [(match_operand:QI 3 "const_mask_operand" "C")]))) + (match_operand:SI 2 "address_operand" "ZQ"))) + (vec_select: + (match_operand:V_HW_4 0 "register_operand" "v") + (parallel [(match_dup 3)])))] "TARGET_VX && TARGET_64BIT && UINTVAL (operands[3]) < 4" "vscef\t%v0,%O2(%v1,%R2),%3" [(set_attr "op_type" "VRV")]) @@ -455,12 +456,13 @@ (define_insn "vec_scatter_element_SI" [(set (mem: (plus:SI (subreg:SI - (unspec: [(match_operand:V_HW_2 1 "register_operand" "v") - (match_operand:QI 3 "const_mask_operand" "C")] - UNSPEC_VEC_EXTRACT) 4) - (match_operand:SI 2 "address_operand" "ZQ"))) - (unspec: [(match_operand:V_HW_2 0 "register_operand" "v") - (match_dup 3)] UNSPEC_VEC_EXTRACT))] + (vec_select: + (match_operand: 1 "register_operand" "v") + (parallel [(match_operand:QI 3 "const_mask_operand" "C")])) 4) + (match_operand:SI 2 "address_operand" "ZQ"))) + (vec_select: + (match_operand:V_HW_2 0 "register_operand" "v") + (parallel [(match_dup 3)])))] "TARGET_VX && !TARGET_64BIT && UINTVAL (operands[3]) < GET_MODE_NUNITS (mode)" "vsce\t%v0,%O2(%v1,%R2),%3" [(set_attr "op_type" "VRV")]) @@ -469,13 +471,14 @@ ; vscef, vsceg (define_insn "vec_scatter_element_" [(set (mem: - (plus: (unspec: - [(match_operand: 1 "register_operand" "v") - (match_operand:QI 3 "const_mask_operand" "C")] - UNSPEC_VEC_EXTRACT) - (match_operand:DI 2 "address_operand" "ZQ"))) - (unspec: [(match_operand:V_HW_32_64 0 "register_operand" "v") - (match_dup 3)] UNSPEC_VEC_EXTRACT))] + (plus: + (vec_select: + (match_operand: 1 "register_operand" "v") + (parallel [(match_operand:QI 3 "const_mask_operand" "C")])) + (match_operand:DI 2 "address_operand" "ZQ"))) + (vec_select: + (match_operand:V_HW_32_64 0 "register_operand" "v") + (parallel [(match_dup 3)])))] "TARGET_VX && UINTVAL (operands[3]) < GET_MODE_NUNITS (mode)" "vsce\t%v0,%O2(%v1,%R2),%3" [(set_attr "op_type" "VRV")]) @@ -1889,9 +1892,11 @@ (const_int VEC_RND_CURRENT)] UNSPEC_VEC_VFLR)) (set (match_operand:SF 1 "memory_operand" "") - (unspec:SF [(match_dup 2) (const_int 0)] UNSPEC_VEC_EXTRACT)) + (vec_select:SF (match_dup 2) + (parallel [(const_int 0)]))) (set (match_dup 3) - (unspec:SF [(match_dup 2) (const_int 2)] UNSPEC_VEC_EXTRACT))] + (vec_select:SF (match_dup 2) + (parallel [(const_int 2)])))] "TARGET_VX" { operands[2] = gen_reg_rtx (V4SFmode); @@ -2300,10 +2305,10 @@ ; *a = vec_revb (b)[1]; get-element-bswap-4.c ; vstebrh, vstebrf, vstebrg (define_insn "*vec_extract_bswap_vec" - [(set (match_operand: 0 "memory_operand" "=R") - (unspec: [(bswap:V_HW_HSD (match_operand:V_HW_HSD 1 "register_operand" "v")) - (match_operand:SI 2 "const_int_operand" "C")] - UNSPEC_VEC_EXTRACT))] + [(set (match_operand: 0 "memory_operand" "=R") + (vec_select: + (bswap:V_HW_HSD (match_operand:V_HW_HSD 1 "register_operand" "v")) + (parallel [(match_operand:SI 2 "const_int_operand" "C")])))] "TARGET_VXE2 && UINTVAL (operands[2]) < GET_MODE_NUNITS (mode)" "vstebr\t%v1,%0,%2" [(set_attr "op_type" "VRX")]) @@ -2312,11 +2317,11 @@ ; *a = __builtin_bswap32 (b[1]); get-element-bswap-2.c ; vstebrh, vstebrf, vstebrg (define_insn "*vec_extract_bswap_elem" - [(set (match_operand: 0 "memory_operand" "=R") + [(set (match_operand: 0 "memory_operand" "=R") (bswap: - (unspec: [(match_operand:V_HW_HSD 1 "register_operand" "v") - (match_operand:SI 2 "const_int_operand" "C")] - UNSPEC_VEC_EXTRACT)))] + (vec_select: + (match_operand:V_HW_HSD 1 "register_operand" "v") + (parallel [(match_operand:SI 2 "const_int_operand" "C")]))))] "TARGET_VXE2 && UINTVAL (operands[2]) < GET_MODE_NUNITS (mode)" "vstebr\t%v1,%0,%2" [(set_attr "op_type" "VRX")])