From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2093) id 81CAD38362CE; Thu, 1 Sep 2022 02:04:03 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 81CAD38362CE DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1661997843; bh=pqWqNpeVQChnT17giJGJCSw4k3PL/+wRGd4T2nzUBYY=; h=From:To:Subject:Date:From; b=KYTlQP+s4XzesixDsuhQTjm8XhuGGYsmiTYYoI5AmL57NF7/DVp176P87vHNh+7ZE p+E7VQeEFNCifebKmgCtfVDLinadfXzbLvluh2dPOaPV8FihkGDYNDWprlfQ3rD8ua qdIik3EEnpXkDG6By3gEQVgk6zWAfEYaIvZy1zFw= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Kito Cheng To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-2326] RISC-V: Fix riscv_vector_chunks configuration according to TARGET_MIN_VLEN X-Act-Checkin: gcc X-Git-Author: zhongjuzhe X-Git-Refname: refs/heads/master X-Git-Oldrev: 542c60c4fb557ec437e3d20634fd59a61d619ac3 X-Git-Newrev: e9f827d79102001d5f0593f0f9e01ab72b2aec9a Message-Id: <20220901020403.81CAD38362CE@sourceware.org> Date: Thu, 1 Sep 2022 02:04:03 +0000 (GMT) List-Id: https://gcc.gnu.org/g:e9f827d79102001d5f0593f0f9e01ab72b2aec9a commit r13-2326-ge9f827d79102001d5f0593f0f9e01ab72b2aec9a Author: zhongjuzhe Date: Tue Aug 30 09:50:24 2022 +0800 RISC-V: Fix riscv_vector_chunks configuration according to TARGET_MIN_VLEN gcc/ChangeLog: * config/riscv/riscv.cc (riscv_convert_vector_bits): Change configuration according to TARGET_MIN_VLEN. * config/riscv/riscv.h (UNITS_PER_FP_REG): Fix comment. Diff: --- gcc/config/riscv/riscv.cc | 13 +++++++------ gcc/config/riscv/riscv.h | 2 +- 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 4d439e15392..5e68fccbb9e 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -5219,22 +5219,23 @@ riscv_init_machine_status (void) static poly_uint16 riscv_convert_vector_bits (void) { - /* The runtime invariant is only meaningful when vector is enabled. */ + /* The runtime invariant is only meaningful when TARGET_VECTOR is enabled. */ if (!TARGET_VECTOR) return 0; - if (TARGET_VECTOR_ELEN_64 || TARGET_VECTOR_ELEN_FP_64) + if (TARGET_MIN_VLEN > 32) { - /* When targetting Zve64* (ELEN = 64) extensions, we should use 64-bit - chunk size. Runtime invariant: The single indeterminate represent the + /* When targetting minimum VLEN > 32, we should use 64-bit chunk size. + Otherwise we can not include SEW = 64bits. + Runtime invariant: The single indeterminate represent the number of 64-bit chunks in a vector beyond minimum length of 64 bits. Thus the number of bytes in a vector is 8 + 8 * x1 which is - riscv_vector_chunks * 8 = poly_int (8, 8). */ + riscv_vector_chunks * 8 = poly_int (8, 8). */ riscv_bytes_per_vector_chunk = 8; } else { - /* When targetting Zve32* (ELEN = 32) extensions, we should use 32-bit + /* When targetting minimum VLEN = 32, we should use 32-bit chunk size. Runtime invariant: The single indeterminate represent the number of 32-bit chunks in a vector beyond minimum length of 32 bits. Thus the number of bytes in a vector is 4 + 4 * x1 which is diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index 1d8139c2c9b..29582f7c545 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -160,7 +160,7 @@ ASM_MISA_SPEC /* The `Q' extension is not yet supported. */ #define UNITS_PER_FP_REG (TARGET_DOUBLE_FLOAT ? 8 : 4) -/* Size per vector register. For zve32*, size = poly (4, 4). Otherwise, size = poly (8, 8). */ +/* Size per vector register. For VLEN = 32, size = poly (4, 4). Otherwise, size = poly (8, 8). */ #define UNITS_PER_V_REG (riscv_vector_chunks * riscv_bytes_per_vector_chunk) /* The largest type that can be passed in floating-point registers. */