From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 7886) id 8C8943858CDB; Mon, 5 Sep 2022 06:40:52 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 8C8943858CDB DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1662360052; bh=VmJnTBN66uOyW/tRaYlpwIkpcnwCbVSJyia0ttJtds0=; h=From:To:Subject:Date:From; b=bcFSBKa5AhBLo3cnEqWvsh9N2ukEvfH9cdJcNU72ILthNAVannbZmG5T+c3+Stsa+ kJoAeJ+2oS05uJCQQHLAKwt0Bp3qEIAFl/l6KfAdSFdGzIgCFzPbhFtt3rEvRKgwZx +V+7gqrd3rHu27vJj3Tu/xzroUhsNTQ2mhoPwcTM= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Kong Lingling To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-2400] x86: Handle V8BF in expand_vec_perm_broadcast_1 X-Act-Checkin: gcc X-Git-Author: konglin1 X-Git-Refname: refs/heads/master X-Git-Oldrev: 5f3228935e27780430a8a1504c2fa4a1ff978594 X-Git-Newrev: 092763fd0c069f3a7c05a65238d3815e8daab76b Message-Id: <20220905064052.8C8943858CDB@sourceware.org> Date: Mon, 5 Sep 2022 06:40:52 +0000 (GMT) List-Id: https://gcc.gnu.org/g:092763fd0c069f3a7c05a65238d3815e8daab76b commit r13-2400-g092763fd0c069f3a7c05a65238d3815e8daab76b Author: konglin1 Date: Mon Sep 5 14:38:03 2022 +0800 x86: Handle V8BF in expand_vec_perm_broadcast_1 gcc/ChangeLog: PR target/106742 * config/i386/i386-expand.cc (ix86_expand_vector_init_duplicate): Handle V8BF mode. (expand_vec_perm_broadcast_1): Ditto. * config/i386/sse.md (avx512fmaskhalfmode): Add BF vector mode. (vec_set_0): Add @ to it. (@vec_set_0): Ditto. (vec_interleave_high): Ditto. (@vec_interleave_high): Ditto. (vec_interleave_low): Ditto. (@vec_interleave_low): Ditto. * config/i386/subst.md (SUBST_V): Add BF vector mode. gcc/testsuite/ChangeLog: * gcc.target/i386/pr106742.c: New test. Diff: --- gcc/config/i386/i386-expand.cc | 15 +++++++++------ gcc/config/i386/sse.md | 7 ++++--- gcc/config/i386/subst.md | 1 + gcc/testsuite/gcc.target/i386/pr106742.c | 10 ++++++++++ 4 files changed, 24 insertions(+), 9 deletions(-) diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc index 836ebc82d67..d7b49c99dc8 100644 --- a/gcc/config/i386/i386-expand.cc +++ b/gcc/config/i386/i386-expand.cc @@ -15034,11 +15034,12 @@ ix86_expand_vector_init_duplicate (bool mmx_ok, machine_mode mode, dperm.op0 = dperm.op1 = gen_reg_rtx (mode); dperm.one_operand_p = true; - if (mode == V8HFmode) + if (mode == V8HFmode || mode == V8BFmode) { - tmp1 = force_reg (HFmode, val); + tmp1 = force_reg (GET_MODE_INNER (mode), val); tmp2 = gen_reg_rtx (mode); - emit_insn (gen_vec_setv8hf_0 (tmp2, CONST0_RTX (mode), tmp1)); + emit_insn (maybe_gen_vec_set_0 (mode, tmp2, + CONST0_RTX (mode), tmp1)); tmp1 = gen_lowpart (mode, tmp2); } else @@ -21826,21 +21827,23 @@ expand_vec_perm_broadcast_1 (struct expand_vec_perm_d *d) return true; case E_V8HFmode: + case E_V8BFmode: /* This can be implemented via interleave and pshufd. */ if (d->testing_p) return true; + rtx (*maybe_gen) (machine_mode, int, rtx, rtx, rtx); if (elt >= nelt2) { - gen = gen_vec_interleave_highv8hf; + maybe_gen = maybe_gen_vec_interleave_high; elt -= nelt2; } else - gen = gen_vec_interleave_lowv8hf; + maybe_gen = maybe_gen_vec_interleave_low; nelt2 /= 2; dest = gen_reg_rtx (vmode); - emit_insn (gen (dest, op0, op0)); + emit_insn (maybe_gen (vmode, 1, dest, op0, op0)); vmode = V4SImode; op0 = gen_lowpart (vmode, dest); diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 259048481b6..72acf0b3e23 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -984,6 +984,7 @@ (V16SI "QI") (V8SI "QI") (V4SI "QI") (V8DI "QI") (V4DI "QI") (V2DI "QI") (V32HF "HI") (V16HF "QI") (V8HF "QI") + (V32BF "HI") (V16BF "QI") (V8BF "QI") (V16SF "QI") (V8SF "QI") (V4SF "QI") (V8DF "QI") (V4DF "QI") (V2DF "QI")]) @@ -10712,7 +10713,7 @@ ] (symbol_ref "true")))]) -(define_insn "vec_set_0" +(define_insn "@vec_set_0" [(set (match_operand:V8_128 0 "register_operand" "=v,v,v,x,x,Yr,*x,x,x,x,v,v") (vec_merge:V8_128 @@ -17895,7 +17896,7 @@ (set_attr "prefix" "maybe_evex") (set_attr "mode" "OI")]) -(define_insn "vec_interleave_high" +(define_insn "@vec_interleave_high" [(set (match_operand:V8_128 0 "register_operand" "=x,Yw") (vec_select:V8_128 (vec_concat: @@ -17963,7 +17964,7 @@ (set_attr "prefix" "maybe_evex") (set_attr "mode" "OI")]) -(define_insn "vec_interleave_low" +(define_insn "@vec_interleave_low" [(set (match_operand:V8_128 0 "register_operand" "=x,Yw") (vec_select:V8_128 (vec_concat: diff --git a/gcc/config/i386/subst.md b/gcc/config/i386/subst.md index 0b7588237fe..e169282fbbc 100644 --- a/gcc/config/i386/subst.md +++ b/gcc/config/i386/subst.md @@ -25,6 +25,7 @@ V16SI V8SI V4SI V8DI V4DI V2DI V32HF V16HF V8HF + V32BF V16BF V8BF V16SF V8SF V4SF V8DF V4DF V2DF]) diff --git a/gcc/testsuite/gcc.target/i386/pr106742.c b/gcc/testsuite/gcc.target/i386/pr106742.c new file mode 100644 index 00000000000..36ac93c9623 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr106742.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-msse2 -mno-sse4 -O1" } */ +typedef __bf16 v8bf __attribute__ ((__vector_size__ (16))); + +v8bf +vec_init_dup_v8bf (__bf16 a1) +{ + return __extension__ (v8bf) { a1, a1, a1, a1, a1, a1, a1, a1 }; +} +/* { dg-final { scan-assembler-times "pinsrw" 1} } */