From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2093) id 598A23858CDA; Mon, 5 Sep 2022 13:32:35 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 598A23858CDA DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1662384755; bh=J/cF4uolDW6t/4gujESck9/kJsz0hCjCkoV2l0EFwE8=; h=From:To:Subject:Date:From; b=eAzzOJI56LW8TgE8taG0/hgW9tvGFCG3r8Nvx59ff/so0Q+Iq8xY2V2hg2Wt8N6mc ryb0X+AJJuuAcdUDFIGYZqBJe6ujDcEItXdZ2m1QOK8B5pbJ2CTrL0CZkpUWaRjBCy kw/8vyMcCZhreoikJB4fNrBz3TkSnWQ2Lj7txU0o= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Kito Cheng To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-2438] RISC-V: Support Zmmul extension X-Act-Checkin: gcc X-Git-Author: LiaoShihua X-Git-Refname: refs/heads/master X-Git-Oldrev: 178447296423ff7e1072621185438c45ab5b0a1d X-Git-Newrev: 77e8e405a770bc40b304cfa55081575cf88f2b31 Message-Id: <20220905133235.598A23858CDA@sourceware.org> Date: Mon, 5 Sep 2022 13:32:35 +0000 (GMT) List-Id: https://gcc.gnu.org/g:77e8e405a770bc40b304cfa55081575cf88f2b31 commit r13-2438-g77e8e405a770bc40b304cfa55081575cf88f2b31 Author: LiaoShihua Date: Wed Jul 13 10:13:26 2022 +0800 RISC-V: Support Zmmul extension gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add Zmmul. * config/riscv/riscv-opts.h (MASK_ZMMUL): New. (TARGET_ZMMUL): Ditto. * config/riscv/riscv.cc (riscv_option_override):Ditto. * config/riscv/riscv.md: Add Zmmul * config/riscv/riscv.opt: Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/zmmul-1.c: New test. * gcc.target/riscv/zmmul-2.c: New test. Diff: --- gcc/common/config/riscv/riscv-common.cc | 4 ++++ gcc/config/riscv/riscv-opts.h | 3 +++ gcc/config/riscv/riscv.cc | 8 ++++++-- gcc/config/riscv/riscv.md | 28 ++++++++++++++-------------- gcc/config/riscv/riscv.opt | 3 +++ gcc/testsuite/gcc.target/riscv/zmmul-1.c | 20 ++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/zmmul-2.c | 20 ++++++++++++++++++++ 7 files changed, 70 insertions(+), 16 deletions(-) diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index cb3a5d270df..120a0384686 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -200,6 +200,8 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"zfh", ISA_SPEC_CLASS_NONE, 1, 0}, {"zfhmin", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zmmul", ISA_SPEC_CLASS_NONE, 1, 0}, + /* Terminate the list. */ {NULL, ISA_SPEC_CLASS_NONE, 0, 0} }; @@ -1214,6 +1216,8 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"zfhmin", &gcc_options::x_riscv_zf_subext, MASK_ZFHMIN}, {"zfh", &gcc_options::x_riscv_zf_subext, MASK_ZFH}, + {"zmmul", &gcc_options::x_riscv_zm_subext, MASK_ZMMUL}, + {NULL, NULL, 0} }; diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index 85e869e62e3..55e0bc0a0e9 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -159,6 +159,9 @@ enum stack_protector_guard { #define TARGET_ZFHMIN ((riscv_zf_subext & MASK_ZFHMIN) != 0) #define TARGET_ZFH ((riscv_zf_subext & MASK_ZFH) != 0) +#define MASK_ZMMUL (1 << 0) +#define TARGET_ZMMUL ((riscv_zm_subext & MASK_ZMMUL) != 0) + /* Bit of riscv_zvl_flags will set contintuly, N-1 bit will set if N-bit is set, e.g. MASK_ZVL64B has set then MASK_ZVL32B is set, so we can use popcount to caclulate the minimal VLEN. */ diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 675d92c0961..b5252b41df7 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -5277,10 +5277,14 @@ riscv_option_override (void) /* The presence of the M extension implies that division instructions are present, so include them unless explicitly disabled. */ if (TARGET_MUL && (target_flags_explicit & MASK_DIV) == 0) - target_flags |= MASK_DIV; + if(!TARGET_ZMMUL) + target_flags |= MASK_DIV; else if (!TARGET_MUL && TARGET_DIV) error ("%<-mdiv%> requires %<-march%> to subsume the % extension"); - + + if(TARGET_ZMMUL && !TARGET_MUL && TARGET_DIV) + warning (0, "%<-mdiv%> cannot be used when % extension is present"); + /* Likewise floating-point division and square root. */ if (TARGET_HARD_FLOAT && (target_flags_explicit & MASK_FDIV) == 0) target_flags |= MASK_FDIV; diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 2bfab198370..d2dfde28e31 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -743,7 +743,7 @@ [(set (match_operand:SI 0 "register_operand" "=r") (mult:SI (match_operand:SI 1 "register_operand" " r") (match_operand:SI 2 "register_operand" " r")))] - "TARGET_MUL" + "TARGET_ZMMUL || TARGET_MUL" "mul%~\t%0,%1,%2" [(set_attr "type" "imul") (set_attr "mode" "SI")]) @@ -752,7 +752,7 @@ [(set (match_operand:DI 0 "register_operand" "=r") (mult:DI (match_operand:DI 1 "register_operand" " r") (match_operand:DI 2 "register_operand" " r")))] - "TARGET_MUL && TARGET_64BIT" + "TARGET_ZMMUL || TARGET_MUL && TARGET_64BIT" "mul\t%0,%1,%2" [(set_attr "type" "imul") (set_attr "mode" "DI")]) @@ -762,7 +762,7 @@ (mult:GPR (match_operand:GPR 1 "register_operand" " r") (match_operand:GPR 2 "register_operand" " r"))) (label_ref (match_operand 3 "" ""))] - "TARGET_MUL" + "TARGET_ZMMUL || TARGET_MUL" { if (TARGET_64BIT && mode == SImode) { @@ -807,7 +807,7 @@ (mult:GPR (match_operand:GPR 1 "register_operand" " r") (match_operand:GPR 2 "register_operand" " r"))) (label_ref (match_operand 3 "" ""))] - "TARGET_MUL" + "TARGET_ZMMUL || TARGET_MUL" { if (TARGET_64BIT && mode == SImode) { @@ -853,7 +853,7 @@ (sign_extend:DI (mult:SI (match_operand:SI 1 "register_operand" " r") (match_operand:SI 2 "register_operand" " r"))))] - "TARGET_MUL && TARGET_64BIT" + "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT" "mulw\t%0,%1,%2" [(set_attr "type" "imul") (set_attr "mode" "SI")]) @@ -864,7 +864,7 @@ (match_operator:SI 3 "subreg_lowpart_operator" [(mult:DI (match_operand:DI 1 "register_operand" " r") (match_operand:DI 2 "register_operand" " r"))])))] - "TARGET_MUL && TARGET_64BIT" + "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT" "mulw\t%0,%1,%2" [(set_attr "type" "imul") (set_attr "mode" "SI")]) @@ -882,7 +882,7 @@ [(set (match_operand:TI 0 "register_operand") (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand")) (any_extend:TI (match_operand:DI 2 "register_operand"))))] - "TARGET_MUL && TARGET_64BIT" + "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT" { rtx low = gen_reg_rtx (DImode); emit_insn (gen_muldi3 (low, operands[1], operands[2])); @@ -904,7 +904,7 @@ (any_extend:TI (match_operand:DI 2 "register_operand" " r"))) (const_int 64))))] - "TARGET_MUL && TARGET_64BIT" + "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT" "mulh\t%0,%1,%2" [(set_attr "type" "imul") (set_attr "mode" "DI")]) @@ -913,7 +913,7 @@ [(set (match_operand:TI 0 "register_operand") (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand")) (sign_extend:TI (match_operand:DI 2 "register_operand"))))] - "TARGET_MUL && TARGET_64BIT" + "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT" { rtx low = gen_reg_rtx (DImode); emit_insn (gen_muldi3 (low, operands[1], operands[2])); @@ -935,7 +935,7 @@ (sign_extend:TI (match_operand:DI 2 "register_operand" " r"))) (const_int 64))))] - "TARGET_MUL && TARGET_64BIT" + "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT" "mulhsu\t%0,%2,%1" [(set_attr "type" "imul") (set_attr "mode" "DI")]) @@ -946,7 +946,7 @@ (match_operand:SI 1 "register_operand" " r")) (any_extend:DI (match_operand:SI 2 "register_operand" " r"))))] - "TARGET_MUL && !TARGET_64BIT" + "(TARGET_ZMMUL || TARGET_MUL) && !TARGET_64BIT" { rtx temp = gen_reg_rtx (SImode); emit_insn (gen_mulsi3 (temp, operands[1], operands[2])); @@ -965,7 +965,7 @@ (any_extend:DI (match_operand:SI 2 "register_operand" " r"))) (const_int 32))))] - "TARGET_MUL && !TARGET_64BIT" + "(TARGET_ZMMUL || TARGET_MUL) && !TARGET_64BIT" "mulh\t%0,%1,%2" [(set_attr "type" "imul") (set_attr "mode" "SI")]) @@ -977,7 +977,7 @@ (match_operand:SI 1 "register_operand" " r")) (sign_extend:DI (match_operand:SI 2 "register_operand" " r"))))] - "TARGET_MUL && !TARGET_64BIT" + "(TARGET_ZMMUL || TARGET_MUL) && !TARGET_64BIT" { rtx temp = gen_reg_rtx (SImode); emit_insn (gen_mulsi3 (temp, operands[1], operands[2])); @@ -996,7 +996,7 @@ (sign_extend:DI (match_operand:SI 2 "register_operand" " r"))) (const_int 32))))] - "TARGET_MUL && !TARGET_64BIT" + "(TARGET_ZMMUL || TARGET_MUL) && !TARGET_64BIT" "mulhsu\t%0,%2,%1" [(set_attr "type" "imul") (set_attr "mode" "SI")]) diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index fbca91b956c..e3af561c153 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -215,6 +215,9 @@ int riscv_zicmo_subext TargetVariable int riscv_zf_subext +TargetVariable +int riscv_zm_subext + Enum Name(isa_spec_class) Type(enum riscv_isa_spec_class) Supported ISA specs (for use with the -misa-spec= option): diff --git a/gcc/testsuite/gcc.target/riscv/zmmul-1.c b/gcc/testsuite/gcc.target/riscv/zmmul-1.c new file mode 100644 index 00000000000..cdae2cb55df --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zmmul-1.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64iafdc_zmmul -mabi=lp64" } */ +int foo1(int a, int b) +{ + return a*b; +} + +int foo2(int a, int b) +{ + return a/b; +} + +int foo3(int a, int b) +{ + return a%b; +} + +/* { dg-final { scan-assembler-times "mulw\t" 1 } } */ +/* { dg-final { scan-assembler-not "div\t" } } */ +/* { dg-final { scan-assembler-not "rem\t" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/zmmul-2.c b/gcc/testsuite/gcc.target/riscv/zmmul-2.c new file mode 100644 index 00000000000..dc6829da92e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zmmul-2.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32iafdc_zmmul -mabi=ilp32" } */ +int foo1(int a, int b) +{ + return a*b; +} + +int foo2(int a, int b) +{ + return a/b; +} + +int foo3(int a, int b) +{ + return a%b; +} + +/* { dg-final { scan-assembler-times "mul\t" 1 } } */ +/* { dg-final { scan-assembler-not "div\t" } } */ +/* { dg-final { scan-assembler-not "rem\t" } } */ \ No newline at end of file