From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2093) id 206013857036; Mon, 5 Sep 2022 13:46:16 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 206013857036 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1662385576; bh=YfaDjEUQYNnL3za69Bvu6/uwzMndQU3yuy5WiYRXh0I=; h=From:To:Subject:Date:From; b=bFCkJBwIXeHiKXFTRx322OsOfzlgCqBs9dpUkO7PW2PUq3wsemeJ4QefRr46Y+NM3 iCzuR6t1wdLZL6+6Av+/oe7q4cONPrHoEEprPKlZNjtAGaMLYmRQ4poDHATVdz262r 389bA0CQjhcOxOuM22cYN1KCJGQLhmIB6ioQC1i8= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Kito Cheng To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-2440] RISC-V: Fix division instructions for `m` with `zmmul` extension. X-Act-Checkin: gcc X-Git-Author: Kito Cheng X-Git-Refname: refs/heads/master X-Git-Oldrev: 48b9c7d5d329a75d0ceb4e3b26a11bc3b6370f4c X-Git-Newrev: ae97ba1efcd66d73d3631addf4c09f55e12d34f5 Message-Id: <20220905134616.206013857036@sourceware.org> Date: Mon, 5 Sep 2022 13:46:16 +0000 (GMT) List-Id: https://gcc.gnu.org/g:ae97ba1efcd66d73d3631addf4c09f55e12d34f5 commit r13-2440-gae97ba1efcd66d73d3631addf4c09f55e12d34f5 Author: Kito Cheng Date: Mon Sep 5 21:36:45 2022 +0800 RISC-V: Fix division instructions for `m` with `zmmul` extension. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_option_override): Fix wrong condition for MASK_DIV and simplify incompatible checking. * config/riscv/riscv.md (muldi3): Adding parentheses. Diff: --- gcc/config/riscv/riscv.cc | 8 ++------ gcc/config/riscv/riscv.md | 2 +- 2 files changed, 3 insertions(+), 7 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index b5252b41df7..675d92c0961 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -5277,14 +5277,10 @@ riscv_option_override (void) /* The presence of the M extension implies that division instructions are present, so include them unless explicitly disabled. */ if (TARGET_MUL && (target_flags_explicit & MASK_DIV) == 0) - if(!TARGET_ZMMUL) - target_flags |= MASK_DIV; + target_flags |= MASK_DIV; else if (!TARGET_MUL && TARGET_DIV) error ("%<-mdiv%> requires %<-march%> to subsume the % extension"); - - if(TARGET_ZMMUL && !TARGET_MUL && TARGET_DIV) - warning (0, "%<-mdiv%> cannot be used when % extension is present"); - + /* Likewise floating-point division and square root. */ if (TARGET_HARD_FLOAT && (target_flags_explicit & MASK_FDIV) == 0) target_flags |= MASK_FDIV; diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index d2dfde28e31..014206fb8bd 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -752,7 +752,7 @@ [(set (match_operand:DI 0 "register_operand" "=r") (mult:DI (match_operand:DI 1 "register_operand" " r") (match_operand:DI 2 "register_operand" " r")))] - "TARGET_ZMMUL || TARGET_MUL && TARGET_64BIT" + "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT" "mul\t%0,%1,%2" [(set_attr "type" "imul") (set_attr "mode" "DI")])