From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1592) id E6860385AC1B; Mon, 5 Sep 2022 18:02:20 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org E6860385AC1B DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1662400940; bh=FulnK5xMdAGLsvGKX4gDLhw6ZTqcbmyF3jYFtDIHN3Q=; h=From:To:Subject:Date:From; b=sbqIN3Ob3sXswfuKgfGKTNf0Pdd8acQaTLP/QV3OcxIj+cXwX1YCuMvgPMpN5+ago qRWrMMHTvSYGztZjffBfWQts+iq5NiEuou5z0Um4tDjOroK0blFfZdEUccM+Zk6+oM 6F0RrK7NVx+UnRzayEhwLEh0J940hFs//Z4HaiA8= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Alexander Monakov To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-2448] i386: avoid zero extension for crc32q X-Act-Checkin: gcc X-Git-Author: Alexander Monakov X-Git-Refname: refs/heads/master X-Git-Oldrev: 8492f7dd51aff17fd755c9f9dd4dc5874ddd6dec X-Git-Newrev: 810d9815249451f477d4cbc67b8e4a0819c37faa Message-Id: <20220905180220.E6860385AC1B@sourceware.org> Date: Mon, 5 Sep 2022 18:02:20 +0000 (GMT) List-Id: https://gcc.gnu.org/g:810d9815249451f477d4cbc67b8e4a0819c37faa commit r13-2448-g810d9815249451f477d4cbc67b8e4a0819c37faa Author: Alexander Monakov Date: Tue Aug 23 18:42:24 2022 +0300 i386: avoid zero extension for crc32q The crc32q instruction takes 64-bit operands, but ignores high 32 bits of the destination operand, and zero-extends the result from 32 bits. Let's model this in the RTL pattern to avoid zero-extension when the _mm_crc32_u64 intrinsic is used with a 32-bit type. PR target/106453 gcc/ChangeLog: * config/i386/i386.md (sse4_2_crc32di): Model that only low 32 bits of operand 0 are consumed, and the result is zero-extended to 64 bits. gcc/testsuite/ChangeLog: * gcc.target/i386/pr106453.c: New test. Diff: --- gcc/config/i386/i386.md | 9 +++++---- gcc/testsuite/gcc.target/i386/pr106453.c | 13 +++++++++++++ 2 files changed, 18 insertions(+), 4 deletions(-) diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 1aef1af594d..1be9b669909 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -23823,10 +23823,11 @@ (define_insn "sse4_2_crc32di" [(set (match_operand:DI 0 "register_operand" "=r") - (unspec:DI - [(match_operand:DI 1 "register_operand" "0") - (match_operand:DI 2 "nonimmediate_operand" "rm")] - UNSPEC_CRC32))] + (zero_extend:DI + (unspec:SI + [(match_operand:SI 1 "register_operand" "0") + (match_operand:DI 2 "nonimmediate_operand" "rm")] + UNSPEC_CRC32)))] "TARGET_64BIT && TARGET_CRC32" "crc32{q}\t{%2, %0|%0, %2}" [(set_attr "type" "sselog1") diff --git a/gcc/testsuite/gcc.target/i386/pr106453.c b/gcc/testsuite/gcc.target/i386/pr106453.c new file mode 100644 index 00000000000..bd2e7282cf6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr106453.c @@ -0,0 +1,13 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mcrc32 -dp" } */ +/* { dg-final { scan-assembler-not "zero_extendsidi" } } */ + +#include +#include + +uint32_t f(uint32_t c, uint64_t *p, size_t n) +{ + for (size_t i = 0; i < n; i++) + c = _mm_crc32_u64(c, p[i]); + return c; +}