From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1130) id 40A963858C00; Wed, 7 Sep 2022 09:52:14 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 40A963858C00 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1662544334; bh=3pqOYp6h/0Al/P5hKjelfrQ8PaUZGQ1RcM6W1YFybRg=; h=From:To:Subject:Date:From; b=hn1BYxwWLBojrfvHs1EXYw4eUMgweanGSI86//IZR2ylsJBQt8SDwS2wiPOmVZOmH 2IfEN6JjwFOcp4REtjUiBzoasPcW4kvFt2S90NfkSV7vw4BaI5SO1Z8KO9GXc3GUux B7seQQE1Cd4CuWKkPnehAq47ogLtfUX2V/E7mEig= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Richard Sandiford To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-2511] aarch64: Prevent FPR register asms for +nofp X-Act-Checkin: gcc X-Git-Author: Richard Sandiford X-Git-Refname: refs/heads/trunk X-Git-Oldrev: 0067ba052b976431c49d6a86f2c9ede9938efcdf X-Git-Newrev: f58d5545d6b39cb6534dae105931e92ea9389d1f Message-Id: <20220907095214.40A963858C00@sourceware.org> Date: Wed, 7 Sep 2022 09:52:14 +0000 (GMT) List-Id: https://gcc.gnu.org/g:f58d5545d6b39cb6534dae105931e92ea9389d1f commit r13-2511-gf58d5545d6b39cb6534dae105931e92ea9389d1f Author: Richard Sandiford Date: Wed Sep 7 10:52:03 2022 +0100 aarch64: Prevent FPR register asms for +nofp +nofp disabled the automatic allocation of FPRs, but it didn't stop users from explicitly putting register variables in FPRs. We'd then either report an ICE or generate unsupported instructions. It's still possible (and deliberately redundant) to specify FPRs in clobber lists. gcc/ * config/aarch64/aarch64.cc (aarch64_conditional_register_usage): Disallow use of FPRs in register asms for !TARGET_FLOAT. gcc/testsuite/ * gcc.target/aarch64/nofp_2.c: New test. Diff: --- gcc/config/aarch64/aarch64.cc | 1 + gcc/testsuite/gcc.target/aarch64/nofp_2.c | 19 +++++++++++++++++++ 2 files changed, 20 insertions(+) diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index 566763ce50c..786ede76131 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -19847,6 +19847,7 @@ aarch64_conditional_register_usage (void) { fixed_regs[i] = 1; call_used_regs[i] = 1; + CLEAR_HARD_REG_BIT (operand_reg_set, i); } } if (!TARGET_SVE) diff --git a/gcc/testsuite/gcc.target/aarch64/nofp_2.c b/gcc/testsuite/gcc.target/aarch64/nofp_2.c new file mode 100644 index 00000000000..8a262cc76fa --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/nofp_2.c @@ -0,0 +1,19 @@ +/* { dg-options "" } */ + +#pragma GCC target "+nothing+nofp" + +void +test (void) +{ + register int q0 asm ("q0"); // { dg-error "not general enough" } + register int q1 asm ("q1"); // { dg-error "not general enough" } + asm volatile ("" : "=w" (q0)); + q1 = q0; + asm volatile ("" :: "w" (q1)); +} + +void +ok (void) +{ + asm volatile ("" ::: "q0"); +}