From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1652) id 9234A3858406; Thu, 8 Sep 2022 09:44:37 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 9234A3858406 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1662630277; bh=Po8r5o7A/MkTc9i0+uOd50cXRO+LJy6UnHiAGwOMV0s=; h=From:To:Subject:Date:From; b=Et/n7Dv94Fr9fDYG63r3kxXmXqMnzuwosIOHgkZ7gtBaZ1cZKhMxZQgEA/OyOlURv mnXC1UfopD7MGj+J4Up3l2mr1oGiGouSARS47aT44x4qPeWzNfA9b73h98jLmC6MBG CFnC5pQh6qJ/cD9VQXtiR9lWw/fLZWEW5N/dfODo= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Christophe Lyon To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-2533] arm: Fix constant immediates predicates and constraints for some MVE builtins X-Act-Checkin: gcc X-Git-Author: Christophe Lyon X-Git-Refname: refs/heads/master X-Git-Oldrev: fbb550359beb904f00f22b86b64a47313c0ae45a X-Git-Newrev: c3fb6658c7670e446f2fd00984404d971e416b3c Message-Id: <20220908094437.9234A3858406@sourceware.org> Date: Thu, 8 Sep 2022 09:44:37 +0000 (GMT) List-Id: https://gcc.gnu.org/g:c3fb6658c7670e446f2fd00984404d971e416b3c commit r13-2533-gc3fb6658c7670e446f2fd00984404d971e416b3c Author: Christophe Lyon Date: Tue Sep 6 16:08:36 2022 +0000 arm: Fix constant immediates predicates and constraints for some MVE builtins Several MVE builtins incorrectly use the same predicate/constraint pair for several modes, which does not match the specification. This patch uses the appropriate iterator instead. 2022-09-06 Christophe Lyon gcc/ * config/arm/mve.md (mve_vqshluq_n_s): Use MVE_pred/MVE_constraint instead of mve_imm_7/Ra. (mve_vqshluq_m_n_s): Likewise. (mve_vqrshrnbq_n_): Use MVE_pred3/MVE_constraint3 instead of mve_imm_8/Rb. (mve_vqrshrunbq_n_s): Likewise. (mve_vqrshrntq_n_): Likewise. (mve_vqrshruntq_n_s): Likewise. (mve_vrshrnbq_n_): Likewise. (mve_vrshrntq_n_): Likewise. (mve_vqrshrnbq_m_n_): Likewise. (mve_vqrshrntq_m_n_): Likewise. (mve_vrshrnbq_m_n_): Likewise. (mve_vrshrntq_m_n_): Likewise. (mve_vqrshrunbq_m_n_s): Likewise. (mve_vsriq_n_): Likewise. Diff: --- gcc/config/arm/mve.md | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index c4dec01baac..714178609f7 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -1624,7 +1624,7 @@ [ (set (match_operand:MVE_2 0 "s_register_operand" "=w") (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") - (match_operand:SI 2 "mve_imm_7" "Ra")] + (match_operand:SI 2 "" "")] VQSHLUQ_N_S)) ] "TARGET_HAVE_MVE" @@ -2615,7 +2615,7 @@ (set (match_operand: 0 "s_register_operand" "=w") (unspec: [(match_operand: 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") - (match_operand:SI 3 "mve_imm_8" "Rb")] + (match_operand:SI 3 "" "")] VQRSHRNBQ_N)) ] "TARGET_HAVE_MVE" @@ -2630,7 +2630,7 @@ (set (match_operand: 0 "s_register_operand" "=w") (unspec: [(match_operand: 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") - (match_operand:SI 3 "mve_imm_8" "Rb")] + (match_operand:SI 3 "" "")] VQRSHRUNBQ_N_S)) ] "TARGET_HAVE_MVE" @@ -3570,7 +3570,7 @@ (set (match_operand:MVE_2 0 "s_register_operand" "=w") (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:SI 3 "mve_imm_selective_upto_8" "Rg")] + (match_operand:SI 3 "" "")] VSRIQ_N)) ] "TARGET_HAVE_MVE" @@ -4473,7 +4473,7 @@ (set (match_operand: 0 "s_register_operand" "=w") (unspec: [(match_operand: 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") - (match_operand:SI 3 "mve_imm_8" "Rb")] + (match_operand:SI 3 "" "")] VQRSHRNTQ_N)) ] "TARGET_HAVE_MVE" @@ -4489,7 +4489,7 @@ (set (match_operand: 0 "s_register_operand" "=w") (unspec: [(match_operand: 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") - (match_operand:SI 3 "mve_imm_8" "Rb")] + (match_operand:SI 3 "" "")] VQRSHRUNTQ_N_S)) ] "TARGET_HAVE_MVE" @@ -4777,7 +4777,7 @@ (set (match_operand: 0 "s_register_operand" "=w") (unspec: [(match_operand: 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") - (match_operand:SI 3 "mve_imm_8" "Rb")] + (match_operand:SI 3 "" "")] VRSHRNBQ_N)) ] "TARGET_HAVE_MVE" @@ -4793,7 +4793,7 @@ (set (match_operand: 0 "s_register_operand" "=w") (unspec: [(match_operand: 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") - (match_operand:SI 3 "mve_imm_8" "Rb")] + (match_operand:SI 3 "" "")] VRSHRNTQ_N)) ] "TARGET_HAVE_MVE" @@ -4987,7 +4987,7 @@ (set (match_operand:MVE_2 0 "s_register_operand" "=w") (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:SI 3 "mve_imm_7" "Ra") + (match_operand:SI 3 "" "") (match_operand: 4 "vpr_register_operand" "Up")] VQSHLUQ_M_N_S)) ] @@ -5019,7 +5019,7 @@ (set (match_operand:MVE_2 0 "s_register_operand" "=w") (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:SI 3 "mve_imm_selective_upto_8" "Rg") + (match_operand:SI 3 "" "") (match_operand: 4 "vpr_register_operand" "Up")] VSRIQ_M_N)) ] @@ -6138,7 +6138,7 @@ (set (match_operand: 0 "s_register_operand" "=w") (unspec: [(match_operand: 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") - (match_operand:SI 3 "mve_imm_8" "Rb") + (match_operand:SI 3 "" "") (match_operand: 4 "vpr_register_operand" "Up")] VQRSHRNBQ_M_N)) ] @@ -6155,7 +6155,7 @@ (set (match_operand: 0 "s_register_operand" "=w") (unspec: [(match_operand: 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") - (match_operand:SI 3 "mve_imm_8" "Rb") + (match_operand:SI 3 "" "") (match_operand: 4 "vpr_register_operand" "Up")] VQRSHRNTQ_M_N)) ] @@ -6223,7 +6223,7 @@ (set (match_operand: 0 "s_register_operand" "=w") (unspec: [(match_operand: 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") - (match_operand:SI 3 "mve_imm_8" "Rb") + (match_operand:SI 3 "" "") (match_operand: 4 "vpr_register_operand" "Up")] VRSHRNBQ_M_N)) ] @@ -6240,7 +6240,7 @@ (set (match_operand: 0 "s_register_operand" "=w") (unspec: [(match_operand: 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") - (match_operand:SI 3 "mve_imm_8" "Rb") + (match_operand:SI 3 "" "") (match_operand: 4 "vpr_register_operand" "Up")] VRSHRNTQ_M_N)) ] @@ -6461,7 +6461,7 @@ (set (match_operand: 0 "s_register_operand" "=w") (unspec: [(match_operand: 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") - (match_operand:SI 3 "mve_imm_8" "Rb") + (match_operand:SI 3 "" "") (match_operand: 4 "vpr_register_operand" "Up")] VQRSHRUNBQ_M_N_S)) ]