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From: GCC Administrator <gccadmin@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org, libstdc++-cvs@gcc.gnu.org Subject: [gcc r13-2654] Daily bump. Date: Wed, 14 Sep 2022 00:18:43 +0000 (GMT) [thread overview] Message-ID: <20220914001843.5DDBE3858D1E@sourceware.org> (raw) https://gcc.gnu.org/g:1995a0227d2602718fd0b283a8c7050fdfc701fb commit r13-2654-g1995a0227d2602718fd0b283a8c7050fdfc701fb Author: GCC Administrator <gccadmin@gcc.gnu.org> Date: Wed Sep 14 00:18:07 2022 +0000 Daily bump. Diff: --- gcc/ChangeLog | 142 ++++++++++++++++++++++++++++++++++++++++++++++++ gcc/DATESTAMP | 2 +- gcc/cp/ChangeLog | 26 +++++++++ gcc/testsuite/ChangeLog | 47 ++++++++++++++++ libgomp/ChangeLog | 11 ++++ libstdc++-v3/ChangeLog | 49 +++++++++++++++++ 6 files changed, 276 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 95705a4931a..423cc0add73 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,145 @@ +2022-09-13 Roger Sayle <roger@nextmovesoftware.com> + + PR target/106877 + * reg-stack.cc (move_for_stack_reg): Check for any_malformed_asm + in gcc_assert. + +2022-09-13 Max Filippov <jcmvbkbc@gmail.com> + + Revert: + 2022-09-12 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa.cc (TARGET_CONSTANT_OK_FOR_CPROP_P): + New macro definition. + (xtensa_constant_ok_for_cprop_p): + Implement the hook as mentioned above. + +2022-09-13 Kewen Lin <linkw@linux.ibm.com> + + PR target/104482 + * config/rs6000/rs6000-c.cc (altivec_resolve_overloaded_builtin): Fix + the equality check for argument number, and move this hunk ahead. + +2022-09-13 Kewen.Lin <linkw@gcc.gnu.org> + + PR target/105485 + * config/rs6000/rs6000-builtin.cc (rs6000_gimple_fold_builtin): Add + the handling for unresolved overloaded builtin function. + (rs6000_expand_builtin): Likewise. + +2022-09-13 Kewen Lin <linkw@linux.ibm.com> + + * config/rs6000/rs6000.cc (class rs6000_cost_data): Add new members + m_nstores, m_reduc_factor, m_gather_load and member function + determine_suggested_unroll_factor. + (rs6000_cost_data::update_target_cost_per_stmt): Update for m_nstores, + m_reduc_factor and m_gather_load. + (rs6000_cost_data::determine_suggested_unroll_factor): New function. + (rs6000_cost_data::finish_cost): Use determine_suggested_unroll_factor. + * config/rs6000/rs6000.opt (rs6000-vect-unroll-limit): New parameter. + (rs6000-vect-unroll-issue): Likewise. + (rs6000-vect-unroll-reduc-threshold): Likewise. + * doc/invoke.texi (rs6000-vect-unroll-limit): Document new parameter. + +2022-09-13 Richard Biener <rguenther@suse.de> + + PR middle-end/106909 + * gimple-fold.cc (gimple_fold_call): Clear the ctrl-altering + flag of a unreachable call. + +2022-09-13 Richard Biener <rguenther@suse.de> + + PR tree-optimization/106913 + * tree-ssa-uninit.cc (warn_uninitialized_vars): Do not set + ft_reachable on EXIT_BLOCK. + +2022-09-13 Richard Sandiford <richard.sandiford@arm.com> + + * config/aarch64/aarch64.cc (aarch64_classify_vector_mode): Use + TARGET_FLOAT instead of TARGET_SIMD. + (aarch64_vectorize_related_mode): Restrict ADVSIMD handling to + TARGET_SIMD. + (aarch64_hard_regno_mode_ok): Don't allow tuples of 2 64-bit vectors + in GPRs. + (aarch64_classify_address): Treat little-endian structure moves + like big-endian for TARGET_FLOAT && !TARGET_SIMD. + (aarch64_secondary_memory_needed): New function. + (aarch64_secondary_reload): Handle 128-bit Advanced SIMD vectors + in the same way as TF, TI and TD. + (aarch64_rtx_mult_cost): Restrict ADVSIMD handling to TARGET_SIMD. + (aarch64_rtx_costs): Likewise. + (aarch64_register_move_cost): Treat a pair of 64-bit vectors + separately from a single 128-bit vector. Handle the cost implied + by aarch64_secondary_memory_needed. + (aarch64_simd_valid_immediate): Restrict ADVSIMD handling to + TARGET_SIMD. + (aarch64_expand_vec_perm_const_1): Likewise. + (TARGET_SECONDARY_MEMORY_NEEDED): New macro. + * config/aarch64/iterators.md (VTX): New iterator. + * config/aarch64/aarch64.md (arches): Add fp_q as a synonym of simd. + (arch_enabled): Adjust accordingly. + (@aarch64_reload_mov<TX:mode>): Extend to... + (@aarch64_reload_mov<VTX:mode>): ...this. + * config/aarch64/aarch64-simd.md (mov<mode>): Require TARGET_FLOAT + rather than TARGET_SIMD. + (movmisalign<mode>): Likewise. + (load_pair<DREG:mode><DREG2:mode>): Likewise. + (vec_store_pair<DREG:mode><DREG2:mode>): Likewise. + (load_pair<VQ:mode><VQ2:mode>): Likewise. + (vec_store_pair<VQ:mode><VQ2:mode>): Likewise. + (@aarch64_split_simd_mov<mode>): Likewise. + (aarch64_get_low<mode>): Likewise. + (aarch64_get_high<mode>): Likewise. + (aarch64_get_half<mode>): Likewise. Canonicalize to a move for + lowpart extracts. + (*aarch64_simd_mov<VDMOV:mode>): Require TARGET_FLOAT rather than + TARGET_SIMD. Use different w<-w and r<-w instructions for + !TARGET_SIMD. Disable immediate moves for !TARGET_SIMD but + add an alternative specifically for w<-Z. + (*aarch64_simd_mov<VQMOV:mode>): Require TARGET_FLOAT rather than + TARGET_SIMD. Likewise for the associated define_splits. Disable + FPR moves and immediate moves for !TARGET_SIMD but add an alternative + specifically for w<-Z. + (aarch64_simd_mov_from_<mode>high): Require TARGET_FLOAT rather than + TARGET_SIMD. Restrict the existing alternatives to TARGET_SIMD + but add a new r<-w one for !TARGET_SIMD. + (*aarch64_get_high<mode>): New pattern. + (load_pair_lanes<mode>): Require TARGET_FLOAT rather than TARGET_SIMD. + (store_pair_lanes<mode>): Likewise. + (*aarch64_combine_internal<mode>): Likewise. Restrict existing + w<-w, w<-r and w<-m alternatives to TARGET_SIMD but add a new w<-r + alternative for !TARGET_SIMD. + (*aarch64_combine_internal_be<mode>): Likewise. + (aarch64_combinez<mode>): Require TARGET_FLOAT rather than TARGET_SIMD. + Remove bogus arch attribute. + (*aarch64_combinez_be<mode>): Likewise. + (@aarch64_vec_concat<mode>): Require TARGET_FLOAT rather than + TARGET_SIMD. + (aarch64_combine<mode>): Likewise. + (aarch64_rev_reglist<mode>): Likewise. + (mov<mode>): Likewise. + (*aarch64_be_mov<VSTRUCT_2D:mode>): Extend to TARGET_FLOAT && + !TARGET_SIMD, regardless of endianness. Extend associated + define_splits in the same way, both for this pattern and the + ones below. + (*aarch64_be_mov<VSTRUCT_2Qmode>): Likewise. Restrict w<-w + alternative to TARGET_SIMD. + (*aarch64_be_movoi): Likewise. + (*aarch64_be_movci): Likewise. + (*aarch64_be_movxi): Likewise. + (*aarch64_be_mov<VSTRUCT_4QD:mode>): Extend to TARGET_FLOAT + && !TARGET_SIMD, regardless of endianness. Restrict w<-w alternative + to TARGET_SIMD for tuples of 128-bit vectors. + (*aarch64_be_mov<VSTRUCT_4QD:mode>): Likewise. + * config/aarch64/aarch64-ldpstp.md: Remove TARGET_SIMD condition + from DREG STP peephole. Change TARGET_SIMD to TARGET_FLOAT in + the VQ and VP_2E LDP and STP peepholes. + +2022-09-13 Richard Sandiford <richard.sandiford@arm.com> + + * config/aarch64/aarch64-simd.md (movv8di): Remove TARGET_SIMD + condition. Likewise for the related define_split. Tweak formatting. + 2022-09-12 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> * config/xtensa/xtensa.cc (TARGET_CONSTANT_OK_FOR_CPROP_P): diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 3ab9ae22f92..21befd25789 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20220913 +20220914 diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 61ad2f8bb7e..1b9e4722150 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,29 @@ +2022-09-13 Patrick Palka <ppalka@redhat.com> + + * cp-tree.h (mark_used): Remove single-parameter overload. Add + default argument to the two-parameter overload. + * decl2.cc (mark_used): Likewise. + +2022-09-13 Patrick Palka <ppalka@redhat.com> + + * cp-tree.h (cxx_constant_value): Define two-parameter version + that omits the object parameter. + * decl.cc (build_explicit_specifier): Omit NULL_TREE object + argument to cxx_constant_value. + * except.cc (build_noexcept_spec): Likewise. + * pt.cc (expand_integer_pack): Likewise. + (fold_targs_r): Likewise. + * semantics.cc (finish_if_stmt_cond): Likewise. + +2022-09-13 Patrick Palka <ppalka@redhat.com> + + * decl.cc (build_explicit_specifier): Pass complain to + cxx_constant_value. + * except.cc (build_noexcept_spec): Likewise. + * pt.cc (expand_integer_pack): Likewise. + (tsubst_function_decl): Propagate error_mark_node returned + from build_explicit_specifier. + 2022-09-12 Patrick Palka <ppalka@redhat.com> * call.cc (build_conditional_expr): Adjust calls to diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 2dbed4a35a8..e537acdf0d4 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,50 @@ +2022-09-13 Roger Sayle <roger@nextmovesoftware.com> + + PR target/106877 + * g++.dg/ext/pr106877.C: New test case. + +2022-09-13 Patrick Palka <ppalka@redhat.com> + + * g++.dg/cpp1z/noexcept-type26.C: New test. + * g++.dg/cpp2a/explicit19.C: New test. + * g++.dg/ext/integer-pack6.C: New test. + +2022-09-13 Kewen Lin <linkw@linux.ibm.com> + + PR target/104482 + * gcc.target/powerpc/pr104482.c: New test. + +2022-09-13 Kewen.Lin <linkw@gcc.gnu.org> + + PR target/105485 + * g++.target/powerpc/pr105485.C: New test. + +2022-09-13 Richard Sandiford <richard.sandiford@arm.com> + + * gcc.target/aarch64/ldp_stp_20.c: New test. + * gcc.target/aarch64/ldp_stp_21.c: Likewise. + * gcc.target/aarch64/ldp_stp_22.c: Likewise. + * gcc.target/aarch64/ldp_stp_23.c: Likewise. + * gcc.target/aarch64/ldp_stp_24.c: Likewise. + * gcc.target/aarch64/movv16qi_1.c (gpr_to_gpr): New function. + * gcc.target/aarch64/movv8qi_1.c (gpr_to_gpr): Likewise. + * gcc.target/aarch64/movv16qi_2.c: New test. + * gcc.target/aarch64/movv16qi_3.c: Likewise. + * gcc.target/aarch64/movv2di_1.c: Likewise. + * gcc.target/aarch64/movv2x16qi_1.c: Likewise. + * gcc.target/aarch64/movv2x8qi_1.c: Likewise. + * gcc.target/aarch64/movv3x16qi_1.c: Likewise. + * gcc.target/aarch64/movv3x8qi_1.c: Likewise. + * gcc.target/aarch64/movv4x16qi_1.c: Likewise. + * gcc.target/aarch64/movv4x8qi_1.c: Likewise. + * gcc.target/aarch64/movv8qi_2.c: Likewise. + * gcc.target/aarch64/movv8qi_3.c: Likewise. + * gcc.target/aarch64/vect_unary_2.c: Likewise. + +2022-09-13 Richard Sandiford <richard.sandiford@arm.com> + + * gcc.target/aarch64/acle/ls64_asm_2.c: New test. + 2022-09-12 Patrick Palka <ppalka@redhat.com> PR c++/101906 diff --git a/libgomp/ChangeLog b/libgomp/ChangeLog index 3ff9d25d76b..88e88ab85d1 100644 --- a/libgomp/ChangeLog +++ b/libgomp/ChangeLog @@ -1,3 +1,14 @@ +2022-09-13 Jakub Jelinek <jakub@redhat.com> + + PR libgomp/106906 + * env.c (get_icv_member_addr): Cast false to void * before assigning + it to icv_addr[1], and comment the whole assignment out. + +2022-09-13 Tobias Burnus <tobias@codesourcery.com> + + * libgomp.texi (gcn): Move misplaced -march=sm_30 remark to ... + (nvptx): ... here. + 2022-09-12 Tobias Burnus <tobias@codesourcery.com> * libgomp.texi (Offload-Target Specifics: nvptx): Document diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog index 5ee68604bbf..4f8d8e0fb7a 100644 --- a/libstdc++-v3/ChangeLog +++ b/libstdc++-v3/ChangeLog @@ -1,3 +1,52 @@ +2022-09-13 Patrick Palka <ppalka@redhat.com> + + * include/std/ranges (__detail::__slide_caches_nothing): Define. + (__detail::__slide_caches_last): Define. + (__detail::__slide_caches_first): Define. + (slide_view): Define. + (enable_borrowed_range<slide_view>): Define. + (slide_view::_Iterator): Define. + (slide_view::_Sentinel): Define. + (views::__detail::__can_slide_view): Define. + (views::_Slide, views::slide): Define. + * testsuite/std/ranges/adaptors/slide/1.cc: New test. + +2022-09-13 Patrick Palka <ppalka@redhat.com> + + * include/std/ranges (__detail::__div_ceil): Define. + (chunk_view): Define. + (chunk_view::_OuterIter): Define. + (chunk_view::_OuterIter::value_type): Define. + (chunk_view::_InnerIter): Define. + (chunk_view<_Vp>): Define partial specialization for forward + ranges. + (enable_borrowed_range<chunk_view>): Define. + (chunk_view<_Vp>::_Iterator): Define. + (views::__detail::__can_chunk_view): Define. + (views::_Chunk, views::chunk): Define. + * testsuite/std/ranges/adaptors/chunk/1.cc: New test. + +2022-09-13 Patrick Palka <ppalka@redhat.com> + + * include/std/ranges (join_view::_Iterator::_M_satisfy): + Adjust resetting _M_inner as per LWG 3569. + (join_view::_Iterator::_M_inner): Wrap in std::optional + as per LWG 3569. + (join_view::_Iterator::_Iterator): Relax constraints as + per LWG 3569. + (join_view::_Iterator::operator*): Adjust as per LWG 3569. + (join_view::_Iterator::operator->): Likewise. + (join_view::_Iterator::operator++): Likewise. + (join_view::_Iterator::operator--): Likewise. + (join_view::_Iterator::iter_move): Likewise. + (join_view::_Iterator::iter_swap): Likewise. + * testsuite/std/ranges/adaptors/join.cc (test14): New test. + +2022-09-13 Patrick Palka <ppalka@redhat.com> + + * include/debug/safe_iterator.h (_GLIBCXX_DEBUG_VERIFY_OPERANDS): + Add parentheses to avoid -Wparentheses warning. + 2022-09-12 Patrick Palka <ppalka@redhat.com> PR libstdc++/106320
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