From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1729) id 776263858C2F; Tue, 27 Sep 2022 22:14:04 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 776263858C2F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1664316844; bh=SMYtw5/m3XKN70SByp0PClzw0oFaqRiuo8AQrKm2jxk=; h=From:To:Subject:Date:From; b=TAxHplBPIvzLGuGfJ7CnYgJ3WD9p+YCGYin1p+UJJfGBctYh7caCI4AcOjvjPIeZ/ 3AhuHa/tjoHQNIXFcD6HQEHQbhV/36vSz1e0xtQFvKvtKCnjbgMI9RD/xkPlaqQEhf fOPNhR2O0+x6bt6fhZJEpBX9pZBoJH4kEZ5e1xfA= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Kwok Yeung To: gcc-cvs@gcc.gnu.org Subject: [gcc/devel/omp/gcc-12] amdgcn: Fix instruction generation for exp2 and log2 operations X-Act-Checkin: gcc X-Git-Author: Kwok Cheung Yeung X-Git-Refname: refs/heads/devel/omp/gcc-12 X-Git-Oldrev: f01e3b9dfd81973498c0a71a266e530aeb6f0c97 X-Git-Newrev: b656c03ff8c4803e3af13429e2bec93709946f2f Message-Id: <20220927221404.776263858C2F@sourceware.org> Date: Tue, 27 Sep 2022 22:14:04 +0000 (GMT) List-Id: https://gcc.gnu.org/g:b656c03ff8c4803e3af13429e2bec93709946f2f commit b656c03ff8c4803e3af13429e2bec93709946f2f Author: Kwok Cheung Yeung Date: Tue Sep 27 21:24:55 2022 +0000 amdgcn: Fix instruction generation for exp2 and log2 operations The GCN instructions for the exp2 and log2 operations are v_exp_* and v_log_* respectively, which unfortunately do not line up with the RTL naming convention. To deal with this, a new set of int attributes is now used when generating the assembly for these instructions. 2022-09-27 Kwok Cheung Yeung gcc/ * config/gcn/gcn-valu.md (math_unop_insn): New attribute. (2, 2, 2, 2, *2_insn, *2_insn): Use math_unop_insn to generate assembler output. Diff: --- gcc/ChangeLog.omp | 8 ++++++++ gcc/config/gcn/gcn-valu.md | 20 ++++++++++++++------ 2 files changed, 22 insertions(+), 6 deletions(-) diff --git a/gcc/ChangeLog.omp b/gcc/ChangeLog.omp index ed2073297e7..39e094476c9 100644 --- a/gcc/ChangeLog.omp +++ b/gcc/ChangeLog.omp @@ -1,3 +1,11 @@ +2022-09-27 Kwok Cheung Yeung + + * config/gcn/gcn-valu.md (math_unop_insn): New attribute. + (2, 2, 2, + 2, *2_insn, + *2_insn): Use math_unop_insn to generate + assembler output. + 2022-09-26 Thomas Schwinge Backported from master: diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md index 5c66f4f680b..838ce84dacb 100644 --- a/gcc/config/gcn/gcn-valu.md +++ b/gcc/config/gcn/gcn-valu.md @@ -2312,13 +2312,21 @@ (UNSPEC_SIN "sin") (UNSPEC_COS "cos")]) +(define_int_attr math_unop_insn + [(UNSPEC_FLOOR "floor") + (UNSPEC_CEIL "ceil") + (UNSPEC_EXP2 "exp") + (UNSPEC_LOG2 "log") + (UNSPEC_SIN "sin") + (UNSPEC_COS "cos")]) + (define_insn "2" [(set (match_operand:FP 0 "register_operand" "= v") (unspec:FP [(match_operand:FP 1 "gcn_alu_operand" "vSvB")] MATH_UNOP_1OR2REG))] "" - "v_%i0\t%0, %1" + "v_%i0\t%0, %1" [(set_attr "type" "vop1") (set_attr "length" "8")]) @@ -2328,7 +2336,7 @@ [(match_operand:V_FP 1 "gcn_alu_operand" "vSvB")] MATH_UNOP_1OR2REG))] "" - "v_%i0\t%0, %1" + "v_%i0\t%0, %1" [(set_attr "type" "vop1") (set_attr "length" "8")]) @@ -2338,7 +2346,7 @@ [(match_operand:FP_1REG 1 "gcn_alu_operand" "vSvB")] MATH_UNOP_1REG))] "flag_unsafe_math_optimizations" - "v_%i0\t%0, %1" + "v_%i0\t%0, %1" [(set_attr "type" "vop1") (set_attr "length" "8")]) @@ -2348,7 +2356,7 @@ [(match_operand:V_FP_1REG 1 "gcn_alu_operand" "vSvB")] MATH_UNOP_1REG))] "flag_unsafe_math_optimizations" - "v_%i0\t%0, %1" + "v_%i0\t%0, %1" [(set_attr "type" "vop1") (set_attr "length" "8")]) @@ -2358,7 +2366,7 @@ [(match_operand:FP_1REG 1 "gcn_alu_operand" "vSvB")] MATH_UNOP_TRIG))] "flag_unsafe_math_optimizations" - "v_%i0\t%0, %1" + "v_%i0\t%0, %1" [(set_attr "type" "vop1") (set_attr "length" "8")]) @@ -2368,7 +2376,7 @@ [(match_operand:V_FP_1REG 1 "gcn_alu_operand" "vSvB")] MATH_UNOP_TRIG))] "flag_unsafe_math_optimizations" - "v_%i0\t%0, %1" + "v_%i0\t%0, %1" [(set_attr "type" "vop1") (set_attr "length" "8")])