From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1130) id 0BE4B385840A; Thu, 29 Sep 2022 10:34:23 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 0BE4B385840A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1664447663; bh=dbkEGXvyMVCN7OJW0WU1kXDL++i/j+JLQq9uMGjj92A=; h=From:To:Subject:Date:From; b=ZkfYqmCxh1eETi6F/+NQnHSnn+mVys1N8oIfn9NdTZsOoUH3quXOUKW2qHVhjoA6s KW/C6Zwq4wUD1DRMoksqECe3uh76/QHaoCbBNecbmG1GJPdVHlep8KCcOEQt1eI8gj Q2mEDErJ0AV0m113A0ExtZ/kmmKyP8t2t7W/qFZU= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Richard Sandiford To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-2940] aarch64: Remove AARCH64_FL_RCPC8_4 [PR107025] X-Act-Checkin: gcc X-Git-Author: Richard Sandiford X-Git-Refname: refs/heads/trunk X-Git-Oldrev: 198bb6ed327c74eb2b0450bf978e4e6a64a6406c X-Git-Newrev: 0f244d848cffeda68f0eb4c5bb9c7e629bf2e957 Message-Id: <20220929103423.0BE4B385840A@sourceware.org> Date: Thu, 29 Sep 2022 10:34:23 +0000 (GMT) List-Id: https://gcc.gnu.org/g:0f244d848cffeda68f0eb4c5bb9c7e629bf2e957 commit r13-2940-g0f244d848cffeda68f0eb4c5bb9c7e629bf2e957 Author: Richard Sandiford Date: Thu Sep 29 11:32:53 2022 +0100 aarch64: Remove AARCH64_FL_RCPC8_4 [PR107025] AARCH64_FL_RCPC8_4 is an odd-one-out in that it has no associated entry in aarch64-option-extensions.def. This means that, although it is internally separated from AARCH64_FL_V8_4A, there is no mechanism for turning it on and off individually, independently of armv8.4-a. The only place that the flag was used independently was in the entry for thunderx3t110, which enabled it alongside V8_3A. As noted in PR107025, this means that any use of the extension will fail to assemble. In the PR trail, Andrew suggested removing the core entry. That might be best long-term, but since the barrier for removing command-line options without a deprecation period is very high, this patch instead just drops the flag from the core entry. We'll still produce correct code. gcc/ PR target/107025 * config/aarch64/aarch64.h (oAARCH64_FL_RCPC8_4): Delete. (AARCH64_FL_FOR_V8_4A): Update accordingly. (AARCH64_ISA_RCPC8_4): Use AARCH64_FL_V8_4A directly. * config/aarch64/aarch64-cores.def (thunderx3t110): Remove AARCH64_FL_RCPC8_4. Diff: --- gcc/config/aarch64/aarch64-cores.def | 2 +- gcc/config/aarch64/aarch64.h | 5 ++--- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def index 008b0b8c177..cf500d0a981 100644 --- a/gcc/config/aarch64/aarch64-cores.def +++ b/gcc/config/aarch64/aarch64-cores.def @@ -133,7 +133,7 @@ AARCH64_CORE("tsv110", tsv110, tsv110, V8_2A, AARCH64_FL_CRYPTO | AARCH64_FL_F /* ARMv8.3-A Architecture Processors. */ /* Marvell cores (TX3). */ -AARCH64_CORE("thunderx3t110", thunderx3t110, thunderx3t110, V8_3A, AARCH64_FL_CRYPTO | AARCH64_FL_RCPC | AARCH64_FL_SM4 | AARCH64_FL_SHA3 | AARCH64_FL_F16FML | AARCH64_FL_RCPC8_4, thunderx3t110, 0x43, 0x0b8, 0x0a) +AARCH64_CORE("thunderx3t110", thunderx3t110, thunderx3t110, V8_3A, AARCH64_FL_CRYPTO | AARCH64_FL_RCPC | AARCH64_FL_SM4 | AARCH64_FL_SHA3 | AARCH64_FL_F16FML, thunderx3t110, 0x43, 0x0b8, 0x0a) /* ARMv8.4-A Architecture Processors. */ diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index c275548b18e..8ea8e2a3913 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -173,7 +173,6 @@ #define AARCH64_FL_SM4 (1 << 17) /* Has ARMv8.4-A SM3 and SM4. */ #define AARCH64_FL_SHA3 (1 << 18) /* Has ARMv8.4-a SHA3 and SHA512. */ #define AARCH64_FL_F16FML (1 << 19) /* Has ARMv8.4-a FP16 extensions. */ -#define AARCH64_FL_RCPC8_4 (1 << 20) /* Has ARMv8.4-a RCPC extensions. */ /* Statistical Profiling extensions. */ #define AARCH64_FL_PROFILE (1 << 21) @@ -265,7 +264,7 @@ (AARCH64_FL_FOR_V8_2A | AARCH64_FL_V8_3A | AARCH64_FL_PAUTH) #define AARCH64_FL_FOR_V8_4A \ (AARCH64_FL_FOR_V8_3A | AARCH64_FL_V8_4A | AARCH64_FL_F16FML \ - | AARCH64_FL_DOTPROD | AARCH64_FL_RCPC8_4 | AARCH64_FL_FLAGM) + | AARCH64_FL_DOTPROD | AARCH64_FL_FLAGM) #define AARCH64_FL_FOR_V8_5A \ (AARCH64_FL_FOR_V8_4A | AARCH64_FL_V8_5A \ | AARCH64_FL_SB | AARCH64_FL_SSBS | AARCH64_FL_PREDRES) @@ -313,7 +312,7 @@ #define AARCH64_ISA_SM4 (aarch64_isa_flags & AARCH64_FL_SM4) #define AARCH64_ISA_SHA3 (aarch64_isa_flags & AARCH64_FL_SHA3) #define AARCH64_ISA_F16FML (aarch64_isa_flags & AARCH64_FL_F16FML) -#define AARCH64_ISA_RCPC8_4 (aarch64_isa_flags & AARCH64_FL_RCPC8_4) +#define AARCH64_ISA_RCPC8_4 (aarch64_isa_flags & AARCH64_FL_V8_4A) #define AARCH64_ISA_RNG (aarch64_isa_flags & AARCH64_FL_RNG) #define AARCH64_ISA_V8_5A (aarch64_isa_flags & AARCH64_FL_V8_5A) #define AARCH64_ISA_TME (aarch64_isa_flags & AARCH64_FL_TME)