[gcc r13-2988] RISC-V: Add '-m[no]-csr-check' option in gcc.

[gcc r13-2988] RISC-V: Add '-m[no]-csr-check' option in gcc.

[Kito Cheng]

https://gcc.gnu.org/g:32f86f2b54dc97cb6a40edef421b6a30c3bd1c04

commit r13-2988-g32f86f2b54dc97cb6a40edef421b6a30c3bd1c04
Author: Jiawei <jiawei@iscas.ac.cn>
Date:   Thu Sep 8 09:50:49 2022 +0800

    RISC-V: Add '-m[no]-csr-check' option in gcc.
    
    Add -m[no]-csr-check option in gcc part, when enable -mcsr-check option,
    it will add csr-check in .option section and pass this to assembler.
    
    gcc/ChangeLog:
    
            * config/riscv/riscv.cc (riscv_file_start): New .option.
            * config/riscv/riscv.opt: New options.
            * doc/invoke.texi: New definations.

Diff:
---
 gcc/config/riscv/riscv.cc  | 5 +++++
 gcc/config/riscv/riscv.opt | 6 ++++++
 gcc/doc/invoke.texi        | 6 ++++++
 3 files changed, 17 insertions(+)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 0d618315828..200ad6031fd 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -5440,6 +5440,11 @@ riscv_file_start (void)
   if (! riscv_mrelax)
     fprintf (asm_out_file, "\t.option norelax\n");
 
+  /* If the user specifies "-mcsr-check" on the command line then enable csr
+     check in the assembler.  */
+  if (riscv_mcsr_check)
+    fprintf (asm_out_file, "\t.option csr-check\n");
+
   if (riscv_emit_attribute_p)
     riscv_emit_attribute ();
 }
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index e3af561c153..8923a11a97d 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -132,6 +132,12 @@ Target Bool Var(riscv_mrelax) Init(1)
 Take advantage of linker relaxations to reduce the number of instructions
 required to materialize symbol addresses.
 
+mcsr-check
+Target Bool Var(riscv_mcsr_check) Init(0)
+Enable the CSR checking for the ISA-dependent CRS and the read-only CSR.
+The ISA-dependent CSR are only valid when the specific ISA is set.  The
+read-only CSR can not be written by the CSR instructions.
+
 Mask(64BIT)
 
 Mask(MUL)
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 518bfdf0867..a5dc6377835 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1226,6 +1226,7 @@ See RS/6000 and PowerPC Options.
 -mbig-endian  -mlittle-endian @gol
 -mstack-protector-guard=@var{guard}  -mstack-protector-guard-reg=@var{reg} @gol
 -mstack-protector-guard-offset=@var{offset}}
+-mcsr-check -mno-csr-check @gol
 
 @emph{RL78 Options}
 @gccoptlist{-msim  -mmul=none  -mmul=g13  -mmul=g14  -mallregs @gol
@@ -28605,6 +28606,11 @@ linker relaxations.
 Emit (do not emit) RISC-V attribute to record extra information into ELF
 objects.  This feature requires at least binutils 2.32.
 
+@item -mcsr-check
+@itemx -mno-csr-check
+@opindex mcsr-check
+Enables or disables the CSR checking.
+
 @item -malign-data=@var{type}
 @opindex malign-data
 Control how GCC aligns variables and constants of array, structure, or union