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From: Christophe Lyon <clyon@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-3030] arm: Add missing early clobber to MVE vrev64q_m patterns Date: Mon, 3 Oct 2022 13:13:50 +0000 (GMT) [thread overview] Message-ID: <20221003131350.815FB3858D38@sourceware.org> (raw) https://gcc.gnu.org/g:06aa66af7d0dacc1b247d9e38175e789ef159191 commit r13-3030-g06aa66af7d0dacc1b247d9e38175e789ef159191 Author: Christophe Lyon <christophe.lyon@arm.com> Date: Mon Oct 3 12:26:03 2022 +0200 arm: Add missing early clobber to MVE vrev64q_m patterns Like the non-predicated vrev64q patterns, mve_vrev64q_m_<supf><mode> and mve_vrev64q_m_f<mode> need an early clobber constraint, otherwise we can generate an unpredictable instruction: Warning: 64-bit element size and same destination and source operands makes instruction UNPREDICTABLE when calling vrevq64_m* with the same first and second arguments. OK for trunk? Thanks, Christophe gcc/ChangeLog: * config/arm/mve.md (mve_vrev64q_m_<supf><mode>): Add early clobber. (mve_vrev64q_m_f<mode>): Likewise. gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vrev64q_m_s16-clobber.c: New test. Diff: --- gcc/config/arm/mve.md | 4 ++-- .../arm/mve/intrinsics/vrev64q_m_s16-clobber.c | 17 +++++++++++++++++ 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 714178609f7..62186f124da 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -3503,7 +3503,7 @@ ;; (define_insn "mve_vrev64q_m_<supf><mode>" [ - (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (set (match_operand:MVE_2 0 "s_register_operand" "=&w") (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] @@ -4598,7 +4598,7 @@ ;; (define_insn "mve_vrev64q_m_f<mode>" [ - (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (set (match_operand:MVE_0 0 "s_register_operand" "=&w") (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") (match_operand:MVE_0 2 "s_register_operand" "w") (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s16-clobber.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s16-clobber.c new file mode 100644 index 00000000000..6464c96181d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s16-clobber.c @@ -0,0 +1,17 @@ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, mve_pred16_t p) +{ + return vrev64q_m_s16 (a, a, p); +} + +float16x8_t +foo2 (float16x8_t a, mve_pred16_t p) +{ + return vrev64q_m_f16 (a, a, p); +}
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