From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1383) id 9160B3857C50; Wed, 5 Oct 2022 19:13:04 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 9160B3857C50 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1664997184; bh=TuViMUvVuz0lCdV6z3lFt5t+W+iuUaLBjRMvqGPDP5c=; h=From:To:Subject:Date:From; b=BY9vNaiKjiA39qc5PBJ+/z1cKJmGpnjIFMgpy2IF0VLhPjDOqwVlEIaGmpmqGM0rh H8zecMiJaPEeWL7I6Zwny1zEWIL1TkqHrgTS8dCKa1wouhUzmofB5xWXmy0/bLhkqB crB4pReIGmI00yAVozh2NO1ACI9ONCiidvZiS0ag= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Segher Boessenkool To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-3099] rs6000: Rework vsx_extract_ X-Act-Checkin: gcc X-Git-Author: Segher Boessenkool X-Git-Refname: refs/heads/master X-Git-Oldrev: c3d131531a23c71e09c032d6222d0b5ff0eb8162 X-Git-Newrev: ba3e5a3826be53ecbb7d6044c50878d44640c296 Message-Id: <20221005191304.9160B3857C50@sourceware.org> Date: Wed, 5 Oct 2022 19:13:04 +0000 (GMT) List-Id: https://gcc.gnu.org/g:ba3e5a3826be53ecbb7d6044c50878d44640c296 commit r13-3099-gba3e5a3826be53ecbb7d6044c50878d44640c296 Author: Segher Boessenkool Date: Tue Oct 4 02:50:22 2022 +0000 rs6000: Rework vsx_extract_ Extracting the left and right halfs of a vector are entirely different operations. Things are simpler if they are separate define_insns, and it is easy to get rid of the "wD" constraint use then. This also give the variant that is a no-op copy its own alternative, of length 0 (and this, cost 0, making it more likely RA will choose it. 2022-10-05 Segher Boessenkool * config/rs6000/vsx.md (vsx_extract_): Replace define_insn by a define_expand. Split the contents to... (*vsx_extract__0): ... this. Rewrite. (*vsx_extract__1): ... and this. Rewrite. Diff: --- gcc/config/rs6000/vsx.md | 80 ++++++++++++++++++++++-------------------------- 1 file changed, 37 insertions(+), 43 deletions(-) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 79a759b1ccf..e0e34a78bca 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -3388,59 +3388,53 @@ ;; Optimize cases were we can do a simple or direct move. ;; Or see if we can avoid doing the move at all -(define_insn "vsx_extract_" - [(set (match_operand: 0 "gpc_reg_operand" "=wa, wa, wr, wr") +(define_expand "vsx_extract_" + [(set (match_operand: 0 "gpc_reg_operand") (vec_select: - (match_operand:VSX_D 1 "gpc_reg_operand" "wa, wa, wa, wa") + (match_operand:VSX_D 1 "gpc_reg_operand") (parallel - [(match_operand:QI 2 "const_0_to_1_operand" "wD, n, wD, n")])))] + [(match_operand:QI 2 "const_0_to_1_operand")])))] "VECTOR_MEM_VSX_P (mode)" -{ - int element = INTVAL (operands[2]); - int op0_regno = REGNO (operands[0]); - int op1_regno = REGNO (operands[1]); - int fldDM; - - gcc_assert (IN_RANGE (element, 0, 1)); - gcc_assert (VSX_REGNO_P (op1_regno)); - - if (element == VECTOR_ELEMENT_SCALAR_64BIT) - { - if (op0_regno == op1_regno) - return ASM_COMMENT_START " vec_extract to same register"; - - else if (INT_REGNO_P (op0_regno) && TARGET_DIRECT_MOVE - && TARGET_POWERPC64) - return "mfvsrd %0,%x1"; + "") - else if (FP_REGNO_P (op0_regno) && FP_REGNO_P (op1_regno)) - return "fmr %0,%1"; +(define_insn "*vsx_extract__0" + [(set (match_operand: 0 "gpc_reg_operand" "=wa,wa,wr") + (vec_select: + (match_operand:VSX_D 1 "gpc_reg_operand" "0,wa,wa") + (parallel + [(match_operand:QI 2 "const_0_to_1_operand" "n,n,n")])))] + "VECTOR_MEM_VSX_P (mode) + && INTVAL (operands[2]) == (BYTES_BIG_ENDIAN ? 0 : 1)" +{ + if (which_alternative == 0) + return ASM_COMMENT_START " vec_extract to same register"; - else if (VSX_REGNO_P (op0_regno)) - return "xxlor %x0,%x1,%x1"; + if (which_alternative == 2) + return "mfvsrd %0,%x1"; - else - gcc_unreachable (); - } + return "xxlor %x0,%x1,%x1"; +} + [(set_attr "type" "*,veclogical,mfvsr") + (set_attr "isa" "*,*,p8v") + (set_attr "length" "0,*,*")]) - else if (element == VECTOR_ELEMENT_MFVSRLD_64BIT && INT_REGNO_P (op0_regno) - && TARGET_P9_VECTOR && TARGET_POWERPC64 && TARGET_DIRECT_MOVE) +(define_insn "*vsx_extract__1" + [(set (match_operand: 0 "gpc_reg_operand" "=wa,wr") + (vec_select: + (match_operand:VSX_D 1 "gpc_reg_operand" "wa,wa") + (parallel + [(match_operand:QI 2 "const_0_to_1_operand" "n,n")])))] + "VECTOR_MEM_VSX_P (mode) + && INTVAL (operands[2]) == (BYTES_BIG_ENDIAN ? 1 : 0)" +{ + if (which_alternative == 1) return "mfvsrld %0,%x1"; - else if (VSX_REGNO_P (op0_regno)) - { - fldDM = element << 1; - if (!BYTES_BIG_ENDIAN) - fldDM = 3 - fldDM; - operands[3] = GEN_INT (fldDM); - return "xxpermdi %x0,%x1,%x1,%3"; - } - - else - gcc_unreachable (); + operands[3] = GEN_INT (BYTES_BIG_ENDIAN ? 2 : 3); + return "xxpermdi %x0,%x1,%x1,%3"; } - [(set_attr "type" "veclogical,mfvsr,mfvsr,vecperm") - (set_attr "isa" "*,*,p8v,p9v")]) + [(set_attr "type" "mfvsr,vecperm") + (set_attr "isa" "*,p9v")]) ;; Optimize extracting a single scalar element from memory. (define_insn_and_split "*vsx_extract___load"