From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1816) id A5407383FB86; Thu, 6 Oct 2022 11:12:53 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A5407383FB86 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1665054773; bh=lgzeianE+A7J2vG6mHrtL8iUachLhdOhrLOAYNZ2I4o=; h=From:To:Subject:Date:From; b=Yv2Lmusk7ib4bWb1AoixJD9pbTymKTMjmqX8NVF4MWuIvVoVSOYDqUjSXEDgczZtG Zq5wFgu0AhQexnPGAZqreEAvFKxxGPDqq2qdwpqPsAUdh8hOzBdWtQwcO5dvD5XolV gPFi0Fr8raCyjCd3FS1gatJ/mkyqdl63fZjTgDJE= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Kyrylo Tkachov To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-3130] aarch64: Remove redundant zero-extends with LDAR X-Act-Checkin: gcc X-Git-Author: Kyrylo Tkachov X-Git-Refname: refs/heads/master X-Git-Oldrev: badd1ac23d24664b2258b1db4d49f37a3f60ccca X-Git-Newrev: 33b93ac3f2fb68a2da0d42fd692fe59533f7a84f Message-Id: <20221006111253.A5407383FB86@sourceware.org> Date: Thu, 6 Oct 2022 11:12:53 +0000 (GMT) List-Id: https://gcc.gnu.org/g:33b93ac3f2fb68a2da0d42fd692fe59533f7a84f commit r13-3130-g33b93ac3f2fb68a2da0d42fd692fe59533f7a84f Author: Kyrylo Tkachov Date: Thu Oct 6 12:09:28 2022 +0100 aarch64: Remove redundant zero-extends with LDAR Like other loads in AArch64, the LDARB,LDARH,LDAR instructions clear out the top part of their destination register and we can thus avoid having to explicitly zero-extend it. We were missing a combine pattern that this patch adds. For one of the examples in the testcase we generated: load_uint8_t_ext_uint16_t: adrp x0, .LANCHOR0 add x0, x0, :lo12:.LANCHOR0 ldarb w0, [x0] and w0, w0, 255 ret but now generate: load_uint8_t_ext_uint16_t: adrp x0, .LANCHOR0 add x0, x0, :lo12:.LANCHOR0 ldarb w0, [x0] ret Bootstrapped and tested on aarch64-none-linux-gnu. gcc/ChangeLog: * config/aarch64/atomics.md (*atomic_load_zext): New pattern. gcc/testsuite/ChangeLog: * gcc.target/aarch64/ldar_2.c: New test. Diff: --- gcc/config/aarch64/atomics.md | 17 +++++++++++++++++ gcc/testsuite/gcc.target/aarch64/ldar_2.c | 27 +++++++++++++++++++++++++++ 2 files changed, 44 insertions(+) diff --git a/gcc/config/aarch64/atomics.md b/gcc/config/aarch64/atomics.md index 90487003362..bc95f6d9d15 100644 --- a/gcc/config/aarch64/atomics.md +++ b/gcc/config/aarch64/atomics.md @@ -640,6 +640,23 @@ } ) +(define_insn "*atomic_load_zext" + [(set (match_operand:SD_HSDI 0 "register_operand" "=r") + (zero_extend:SD_HSDI + (unspec_volatile:ALLX + [(match_operand:ALLX 1 "aarch64_sync_memory_operand" "Q") + (match_operand:SI 2 "const_int_operand")] ;; model + UNSPECV_LDA)))] + "GET_MODE_SIZE (mode) > GET_MODE_SIZE (mode)" + { + enum memmodel model = memmodel_from_int (INTVAL (operands[2])); + if (is_mm_relaxed (model) || is_mm_consume (model) || is_mm_release (model)) + return "ldr\t%0, %1"; + else + return "ldar\t%0, %1"; + } +) + (define_insn "atomic_load" [(set (match_operand:ALLI 0 "register_operand" "=r") (unspec_volatile:ALLI diff --git a/gcc/testsuite/gcc.target/aarch64/ldar_2.c b/gcc/testsuite/gcc.target/aarch64/ldar_2.c new file mode 100644 index 00000000000..60b0717271c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/ldar_2.c @@ -0,0 +1,27 @@ +/* Test that the zero-extending patterns for LDAR are used. */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include + +uint8_t v_uint8_t; +uint16_t v_uint16_t; +uint32_t v_uint32_t; +uint64_t v_uint64_t; + +#define FUNC(FROM, TO) \ +TO \ +load_##FROM##_ext_##TO (void) \ +{ \ + return __atomic_load_n (&v_##FROM, __ATOMIC_ACQUIRE); \ +} + +FUNC (uint8_t, uint16_t) +FUNC (uint8_t, uint32_t) +FUNC (uint8_t, uint64_t) +FUNC (uint16_t, uint32_t) +FUNC (uint16_t, uint64_t) +FUNC (uint32_t, uint64_t) + +/* { dg-final { scan-assembler-not {and\tw[0-9+], w[0-9]+, 255} } } */ +/* { dg-final { scan-assembler-not {uxtw\tx[0-9+], w[0-9]+} } } */