From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 9EECE3858D28; Fri, 7 Oct 2022 17:48:34 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 9EECE3858D28 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1665164914; bh=Fn1RIa+gnpBVv8OhYDyr77Hb47PTivz4nAyRzRb3gdc=; h=From:To:Subject:Date:From; b=jxtnv8AzUouFG7ZszJrojGcbS8zPoU8XY5axzHw5zTBL4sRy1X/bYwb4W97u8hiLv R5cyTHpUsxDH6CLCIR9PBjm7+nIQxhnX7ug/7wNOBmH173k+l5pJGErWL32Zk8+BNS FlHakMvQRIyF8XKPiG/AW+3yH7ExHpKzX2MSXok0= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/dmf001)] Add -mcpu=future/-mdmf instrastructure. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/dmf001 X-Git-Oldrev: c509b52ba820b978606ee9b8c1e8928945d2c0c8 X-Git-Newrev: e173162f19142d387c40986e8f0de5492b0ba505 Message-Id: <20221007174834.9EECE3858D28@sourceware.org> Date: Fri, 7 Oct 2022 17:48:34 +0000 (GMT) List-Id: https://gcc.gnu.org/g:e173162f19142d387c40986e8f0de5492b0ba505 commit e173162f19142d387c40986e8f0de5492b0ba505 Author: Michael Meissner Date: Fri Oct 7 13:48:14 2022 -0400 Add -mcpu=future/-mdmf instrastructure. 2022-10-07 Michael Meissner gcc/ * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define __DMF__ if dmf support is enabled. * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS): New macro. (POWERPC_MASKS): Add -mblock-ops-vector-pair and -mdmf. (future cpu): Add -mcpu=future and -mtune=future support. * config/rs6000/rs6000-opts.h (processor_type): Add PROCESSOR_FUTURE. * config/rs6000/rs6000-tables.op: Regenerate. * config/rs6000/rs6000.cc (rs6000_option_override_internal): Add -mcpu=future and -mtune=future support, but for now make them mostly equivalent to power10. Add -mdmf checking. (rs6000_machine_from_flags): Likewise. (rs6000_reassociation_width): Likewise. (rs6000_adjust_cost): Likewise. (rs6000_issue_rate): Likewise. (rs6000_sched_reorder): Likewise. (rs6000_sched_reorder2): Likewise. (rs6000_register_move_cost): Likewise. (rs6000_opt_masks): Add -mdmf. * config/rs6000/rs6000.h (ASM_CPU_SPEC): Add -mcpu=future support. * config/rs6000/rs6000.md (cpu attribute): Add future. (isa attribute): Add dmf. (enabled attribute): Likewise. * config/rs6000/rs6000.opt (-mdmf): New option. Diff: --- gcc/config/rs6000/rs6000-c.cc | 3 +++ gcc/config/rs6000/rs6000-cpus.def | 8 ++++++++ gcc/config/rs6000/rs6000-opts.h | 4 +++- gcc/config/rs6000/rs6000-tables.opt | 3 +++ gcc/config/rs6000/rs6000.cc | 35 +++++++++++++++++++++++++++++++---- gcc/config/rs6000/rs6000.h | 1 + gcc/config/rs6000/rs6000.md | 8 ++++++-- gcc/config/rs6000/rs6000.opt | 4 ++++ 8 files changed, 59 insertions(+), 7 deletions(-) diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc index 56609462629..0a0e4bcd618 100644 --- a/gcc/config/rs6000/rs6000-c.cc +++ b/gcc/config/rs6000/rs6000-c.cc @@ -598,6 +598,9 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags) /* Tell the user if we support the MMA instructions. */ if ((flags & OPTION_MASK_MMA) != 0) rs6000_define_or_undefine_macro (define_p, "__MMA__"); + /* Tell the user if we support the DMF instructions. */ + if ((flags & OPTION_MASK_DMF) != 0) + rs6000_define_or_undefine_macro (define_p, "__DMF__"); /* Whether pc-relative code is being generated. */ if ((flags & OPTION_MASK_PCREL) != 0) rs6000_define_or_undefine_macro (define_p, "__PCREL__"); diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index c3825bcccd8..b402079090f 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -87,6 +87,11 @@ | OTHER_POWER10_MASKS \ | OPTION_MASK_P10_FUSION) +/* Flags for a potential future processor that may or may not be delivered. */ +#define ISA_FUTURE_MASKS (ISA_3_1_MASKS_SERVER \ + | OPTION_MASK_BLOCK_OPS_VECTOR_PAIR \ + | OPTION_MASK_DMF) + /* Flags that need to be turned off if -mno-power9-vector. */ #define OTHER_P9_VECTOR_MASKS (OPTION_MASK_FLOAT128_HW \ | OPTION_MASK_P9_MINMAX) @@ -122,11 +127,13 @@ /* Mask of all options to set the default isa flags based on -mcpu=. */ #define POWERPC_MASKS (OPTION_MASK_ALTIVEC \ + | OPTION_MASK_BLOCK_OPS_VECTOR_PAIR \ | OPTION_MASK_CMPB \ | OPTION_MASK_CRYPTO \ | OPTION_MASK_DFP \ | OPTION_MASK_DIRECT_MOVE \ | OPTION_MASK_DLMZB \ + | OPTION_MASK_DMF \ | OPTION_MASK_EFFICIENT_UNALIGNED_VSX \ | OPTION_MASK_FLOAT128_HW \ | OPTION_MASK_FLOAT128_KEYWORD \ @@ -264,3 +271,4 @@ RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, OPTION_MASK_PPC_GFXOPT RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER | OPTION_MASK_HTM) RS6000_CPU ("rs64", PROCESSOR_RS64A, OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64) +RS6000_CPU ("future", PROCESSOR_FUTURE, MASK_POWERPC64 | ISA_FUTURE_MASKS) diff --git a/gcc/config/rs6000/rs6000-opts.h b/gcc/config/rs6000/rs6000-opts.h index 2333c2e9e66..682788043db 100644 --- a/gcc/config/rs6000/rs6000-opts.h +++ b/gcc/config/rs6000/rs6000-opts.h @@ -67,7 +67,9 @@ enum processor_type PROCESSOR_MPCCORE, PROCESSOR_CELL, PROCESSOR_PPCA2, - PROCESSOR_TITAN + PROCESSOR_TITAN, + + PROCESSOR_FUTURE }; diff --git a/gcc/config/rs6000/rs6000-tables.opt b/gcc/config/rs6000/rs6000-tables.opt index b0df52de679..a5e65b4478a 100644 --- a/gcc/config/rs6000/rs6000-tables.opt +++ b/gcc/config/rs6000/rs6000-tables.opt @@ -197,3 +197,6 @@ Enum(rs6000_cpu_opt_value) String(powerpc64le) Value(55) EnumValue Enum(rs6000_cpu_opt_value) String(rs64) Value(56) +EnumValue +Enum(rs6000_cpu_opt_value) String(future) Value(57) + diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index d2743f7bce6..714dfc1ea4e 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -3742,6 +3742,10 @@ rs6000_option_override_internal (bool global_init_p) gcc_assert (tune_index >= 0); rs6000_tune = processor_target_table[tune_index].processor; + /* For now, make -mtune=future the same as -mtune=power10. */ + if (rs6000_tune == PROCESSOR_FUTURE) + rs6000_tune = PROCESSOR_POWER10; + if (rs6000_cpu == PROCESSOR_PPCE300C2 || rs6000_cpu == PROCESSOR_PPCE300C3 || rs6000_cpu == PROCESSOR_PPCE500MC || rs6000_cpu == PROCESSOR_PPCE500MC64 || rs6000_cpu == PROCESSOR_PPCE5500) @@ -4395,6 +4399,14 @@ rs6000_option_override_internal (bool global_init_p) if (!TARGET_PCREL && TARGET_PCREL_OPT) rs6000_isa_flags &= ~OPTION_MASK_PCREL_OPT; + /* DMF requires MMA. */ + if (TARGET_DMF && !TARGET_MMA) + { + if ((rs6000_isa_flags_explicit & OPTION_MASK_DMF) != 0) + error ("%qs requires %qs", "-mdmf", "-mmma"); + rs6000_isa_flags &= ~OPTION_MASK_DMF; + } + if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET) rs6000_print_isa_options (stderr, 0, "after subtarget", rs6000_isa_flags); @@ -4405,6 +4417,7 @@ rs6000_option_override_internal (bool global_init_p) && rs6000_tune != PROCESSOR_POWER8 && rs6000_tune != PROCESSOR_POWER9 && rs6000_tune != PROCESSOR_POWER10 + && rs6000_tune != PROCESSOR_FUTURE && rs6000_tune != PROCESSOR_PPCA2 && rs6000_tune != PROCESSOR_CELL && rs6000_tune != PROCESSOR_PPC476); @@ -4419,6 +4432,7 @@ rs6000_option_override_internal (bool global_init_p) || rs6000_tune == PROCESSOR_POWER8 || rs6000_tune == PROCESSOR_POWER9 || rs6000_tune == PROCESSOR_POWER10 + || rs6000_tune == PROCESSOR_FUTURE || rs6000_tune == PROCESSOR_PPCE500MC || rs6000_tune == PROCESSOR_PPCE500MC64 || rs6000_tune == PROCESSOR_PPCE5500 @@ -4718,6 +4732,7 @@ rs6000_option_override_internal (bool global_init_p) break; case PROCESSOR_POWER10: + case PROCESSOR_FUTURE: rs6000_cost = &power10_cost; break; @@ -5849,6 +5864,10 @@ rs6000_machine_from_flags (void) if (rs6000_cpu == PROCESSOR_MPCCORE) return "\"821\""; + /* Some future processor. For now, just use power10. */ + if (rs6000_cpu == PROCESSOR_FUTURE) + return "power10"; + #if 0 /* This (and ppc64 below) are disabled here (for now at least) because PROCESSOR_POWERPC, PROCESSOR_POWERPC64, and PROCESSOR_COMMON @@ -10085,6 +10104,7 @@ rs6000_reassociation_width (unsigned int opc ATTRIBUTE_UNUSED, case PROCESSOR_POWER8: case PROCESSOR_POWER9: case PROCESSOR_POWER10: + case PROCESSOR_FUTURE: if (DECIMAL_FLOAT_MODE_P (mode)) return 1; if (VECTOR_MODE_P (mode)) @@ -17872,7 +17892,8 @@ rs6000_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, int cost, /* Separate a load from a narrower, dependent store. */ if ((rs6000_sched_groups || rs6000_tune == PROCESSOR_POWER9 - || rs6000_tune == PROCESSOR_POWER10) + || rs6000_tune == PROCESSOR_POWER10 + || rs6000_tune == PROCESSOR_FUTURE) && GET_CODE (PATTERN (insn)) == SET && GET_CODE (PATTERN (dep_insn)) == SET && MEM_P (XEXP (PATTERN (insn), 1)) @@ -17911,6 +17932,7 @@ rs6000_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, int cost, || rs6000_tune == PROCESSOR_POWER8 || rs6000_tune == PROCESSOR_POWER9 || rs6000_tune == PROCESSOR_POWER10 + || rs6000_tune == PROCESSOR_FUTURE || rs6000_tune == PROCESSOR_CELL) && recog_memoized (dep_insn) && (INSN_CODE (dep_insn) >= 0)) @@ -18485,6 +18507,7 @@ rs6000_issue_rate (void) case PROCESSOR_POWER9: return 6; case PROCESSOR_POWER10: + case PROCESSOR_FUTURE: return 8; default: return 1; @@ -19201,7 +19224,8 @@ rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED, int sched_verbose, load_store_pendulum = 0; /* Do Power10 dependent reordering. */ - if (rs6000_tune == PROCESSOR_POWER10 && last_scheduled_insn) + if ((rs6000_tune == PROCESSOR_POWER10 + || rs6000_tune == PROCESSOR_FUTURE) && last_scheduled_insn) power10_sched_reorder (ready, n_ready - 1); return rs6000_issue_rate (); @@ -19226,7 +19250,8 @@ rs6000_sched_reorder2 (FILE *dump, int sched_verbose, rtx_insn **ready, return power9_sched_reorder2 (ready, *pn_ready - 1); /* Do Power10 dependent reordering. */ - if (rs6000_tune == PROCESSOR_POWER10 && last_scheduled_insn) + if ((rs6000_tune == PROCESSOR_POWER10 + || rs6000_tune == PROCESSOR_FUTURE) && last_scheduled_insn) return power10_sched_reorder (ready, *pn_ready - 1); return cached_can_issue_more; @@ -22441,7 +22466,8 @@ rs6000_register_move_cost (machine_mode mode, allocation a move within the same class might turn out to be a nop. */ if (rs6000_tune == PROCESSOR_POWER9 - || rs6000_tune == PROCESSOR_POWER10) + || rs6000_tune == PROCESSOR_POWER10 + || rs6000_tune == PROCESSOR_FUTURE) ret = 3 * hard_regno_nregs (FIRST_GPR_REGNO, mode); else ret = 4 * hard_regno_nregs (FIRST_GPR_REGNO, mode); @@ -24093,6 +24119,7 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] = { "crypto", OPTION_MASK_CRYPTO, false, true }, { "direct-move", OPTION_MASK_DIRECT_MOVE, false, true }, { "dlmzb", OPTION_MASK_DLMZB, false, true }, + { "dmf", OPTION_MASK_DMF, false, true }, { "efficient-unaligned-vsx", OPTION_MASK_EFFICIENT_UNALIGNED_VSX, false, true }, { "float128", OPTION_MASK_FLOAT128_KEYWORD, false, true }, diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index b4df22b6030..0df5911d852 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -163,6 +163,7 @@ mcpu=e5500: -me5500; \ mcpu=e6500: -me6500; \ mcpu=titan: -mtitan; \ + mcpu=future: -mpower10; \ !mcpu*: %{mpower9-vector: -mpower9; \ mpower8-vector|mcrypto|mdirect-move|mhtm: -mpower8; \ mvsx: -mpower7; \ diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index ad5a4cf2ef8..3e74a8b4343 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -350,11 +350,11 @@ ppc403,ppc405,ppc440,ppc476, ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500, power4,power5,power6,power7,power8,power9,power10, - rs64a,mpccore,cell,ppca2,titan" + rs64a,mpccore,cell,ppca2,titan,future" (const (symbol_ref "(enum attr_cpu) rs6000_tune"))) ;; The ISA we implement. -(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9,p9v,p9kf,p9tf,p10" +(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9,p9v,p9kf,p9tf,p10,dmf" (const_string "any")) ;; Is this alternative enabled for the current CPU/ISA/etc.? @@ -402,6 +402,10 @@ (and (eq_attr "isa" "p10") (match_test "TARGET_POWER10")) (const_int 1) + + (and (eq_attr "isa" "dmf") + (match_test "TARGET_DMF")) + (const_int 1) ] (const_int 0))) ;; If this instruction is microcoded on the CELL processor diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index b63a5d443af..f3e8a0f1755 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -620,6 +620,10 @@ mieee128-constant Target Var(TARGET_IEEE128_CONSTANT) Init(1) Save Generate (do not generate) code that uses the LXVKQ instruction. +mdmf +Target Mask(DMF) Var(rs6000_isa_flags) +Generate (do not generate) DMF instructions. + ; Documented parameters -param=rs6000-vect-unroll-limit=